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phy: exynos-mipi-video: Add support for Exynos 5420 and 5433 SoCs

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This patch adds support for MIPI DPHYs found in Exynos5420-compatible
(5420, 5422 and 5800) and Exynos5433 SoCs. Those SoCs differs from
earlier by different offset of MIPI DPHY registers in PMU controllers
(Exynos 5420-compatible case) or by moving MIPI DPHY reset registers to
separate system register controllers (Exynos 5433 case). In both case
also additional 5th PHY (MIPI CSIS 2) has been added.

Acked-by: Sylwester Nawrocki <[email protected]>
Signed-off-by: Marek Szyprowski <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
This commit is contained in:
Marek Szyprowski authored and Kishon Vijay Abraham I committed 2016-04-30 20:12:30 +05:30
1 parent 97a3042f76
commit 71f5c63c07
3 files changed
+147 -3
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include/linux/mfd/syscon/exynos5-pmu.h
+3
View File
@@ -38,6 +38,9 @@
/* Exynos5433 specific register definitions */
#define EXYNOS5433_USBHOST30_PHY_CONTROL (0x728)
#define EXYNOS5433_MIPI_PHY0_CONTROL (0x710)
#define EXYNOS5433_MIPI_PHY1_CONTROL (0x714)
#define EXYNOS5433_MIPI_PHY2_CONTROL (0x718)
#define EXYNOS5_PHY_ENABLE BIT(0)