From c14bea053775e0c79a6fdd2d1b5a1d9de4fbd7c7 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 7 Oct 2020 17:37:42 -0700 Subject: [PATCH 01/38] memory: tegra: Correct la.reg address of seswr According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field [23:16] of register at address 0x3e0 with a reset value of 0x80 at register 0x3e0, while bit-1 of register 0xb98 is for enable bit of seswr. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-2-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra210.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index 7fb8b5438bf4..088814279616 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .bit = 1, }, .la = { - .reg = 0xb98, + .reg = 0x3e0, .shift = 16, .mask = 0xff, .def = 0x80, From f68ac0e6bd83582b1a8ebf1b76c03eacea25fa49 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 7 Oct 2020 17:37:43 -0700 Subject: [PATCH 02/38] memory: tegra: Correct tegra210_mc_clients def values Some def values are mismatched with Tegra X1 TRM, probably because being copied from tegra124.c file. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-3-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra210.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index 088814279616..e8a7d266802c 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -24,7 +24,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2e8, .shift = 0, .mask = 0xff, - .def = 0xc2, + .def = 0x1e, }, }, { .id = 0x02, @@ -38,7 +38,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2f4, .shift = 0, .mask = 0xff, - .def = 0xc6, + .def = 0x1e, }, }, { .id = 0x03, @@ -52,7 +52,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2e8, .shift = 16, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x04, @@ -66,7 +66,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2f4, .shift = 16, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x05, @@ -80,7 +80,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2ec, .shift = 0, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x06, @@ -94,7 +94,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2f8, .shift = 0, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x0e, @@ -108,7 +108,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2e0, .shift = 0, .mask = 0xff, - .def = 0x13, + .def = 0x2e, }, }, { .id = 0x0f, @@ -136,7 +136,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2f0, .shift = 0, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x11, @@ -150,7 +150,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2fc, .shift = 0, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x15, @@ -380,7 +380,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x350, .shift = 16, .mask = 0xff, - .def = 0x65, + .def = 0x80, }, }, { .id = 0x44, @@ -620,7 +620,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2f0, .shift = 16, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x60, @@ -648,7 +648,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x3bc, .shift = 0, .mask = 0xff, - .def = 0x49, + .def = 0x5a, }, }, { .id = 0x62, @@ -676,7 +676,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x3c4, .shift = 0, .mask = 0xff, - .def = 0x49, + .def = 0x5a, }, }, { .id = 0x64, @@ -956,7 +956,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x3ec, .shift = 16, .mask = 0xff, - .def = 0xff, + .def = 0x80, }, }, { .id = 0x86, From 78e4ea785c0737c906f4830c79d21dc6cb928f68 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 7 Oct 2020 17:37:44 -0700 Subject: [PATCH 03/38] memory: tegra: Sort tegra210_swgroups by reg address Cleanup the list of swgroups (ordering by register address) to prepare for new ones. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-4-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra210.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index e8a7d266802c..b400802c9f14 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { }; static const struct tegra_smmu_swgroup tegra210_swgroups[] = { - { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, - { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 }, { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c }, - { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, + { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, + { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 }, + { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, + { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 }, { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 }, { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 }, - { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, + { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, + { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 }, { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 }, { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c }, - { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, - { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 }, - { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac }, + { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 }, { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 }, { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c }, { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 }, - { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 }, - { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, + { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, + { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac }, { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 }, { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 }, - { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 }, { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc }, + { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 }, { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc }, { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 }, { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 }, From 65abc8ef57009b95fcded5136aed8ccaff46b903 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 7 Oct 2020 17:37:45 -0700 Subject: [PATCH 04/38] dt-bindings: memory: tegra: Add missing swgroups According to Tegra X1 TRM, there are missing swgroups in the tegra210_swgroups list. So this patch adds them in bindings. Note that the TEGRA_SWGROUP_GPU (in list) should be actually TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps TEGRA_SWGROUP_GPU (in list) as it is. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-5-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h index cacf05617e03..5e082547f179 100644 --- a/include/dt-bindings/memory/tegra210-mc.h +++ b/include/dt-bindings/memory/tegra210-mc.h @@ -33,6 +33,16 @@ #define TEGRA_SWGROUP_AXIAP 28 #define TEGRA_SWGROUP_ETR 29 #define TEGRA_SWGROUP_TSECB 30 +#define TEGRA_SWGROUP_NV 31 +#define TEGRA_SWGROUP_NV2 32 +#define TEGRA_SWGROUP_PPCS1 33 +#define TEGRA_SWGROUP_DC1 34 +#define TEGRA_SWGROUP_PPCS2 35 +#define TEGRA_SWGROUP_HC1 36 +#define TEGRA_SWGROUP_SE1 37 +#define TEGRA_SWGROUP_TSEC1 38 +#define TEGRA_SWGROUP_TSECB1 39 +#define TEGRA_SWGROUP_NVDEC1 40 #define TEGRA210_MC_RESET_AFI 0 #define TEGRA210_MC_RESET_AVPC 1 From 21d3cdd0391bb01b348a47ec117eff3b9615d3a9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:40 +0300 Subject: [PATCH 05/38] dt-bindings: memory: tegra20: emc: Correct registers range in example There is superfluous zero in the registers base address and registers size should be twice bigger. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201104164923.21238-5-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index add95367640b..567cffd37f3f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -21,7 +21,7 @@ Example: #address-cells = < 1 >; #size-cells = < 0 >; compatible = "nvidia,tegra20-emc"; - reg = <0x7000f4000 0x200>; + reg = <0x7000f400 0x400>; interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; } From 4cfdad35ae7ed400d7146aeb57d34744ce53e9dc Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:37 +0300 Subject: [PATCH 06/38] clk: tegra: Export Tegra20 EMC kernel symbols We're going to modularize Tegra EMC drivers and some of the EMC-clock driver symbols need to be exported. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201104164923.21238-2-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/clk/tegra/clk-tegra20-emc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20-emc.c b/drivers/clk/tegra/clk-tegra20-emc.c index 03bf0009a33c..dd74b8543bf1 100644 --- a/drivers/clk/tegra/clk-tegra20-emc.c +++ b/drivers/clk/tegra/clk-tegra20-emc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -235,6 +236,7 @@ void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, emc->cb_arg = cb_arg; } } +EXPORT_SYMBOL_GPL(tegra20_clk_set_emc_round_callback); bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw) { @@ -291,3 +293,4 @@ int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same) return 0; } +EXPORT_SYMBOL_GPL(tegra20_clk_prepare_emc_mc_same_freq); From fc4fbf88ecbee88381899b4a7f97c9b52570e91a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:38 +0300 Subject: [PATCH 07/38] soc/tegra: fuse: Export tegra_read_ram_code() The tegra_read_ram_code() is used by EMC drivers and we're going to make these driver modular, hence this function needs to be exported. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201104164923.21238-3-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/soc/tegra/fuse/tegra-apbmisc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index cee207d10024..590c862538d0 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -3,6 +3,7 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include @@ -90,6 +91,7 @@ u32 tegra_read_ram_code(void) return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT; } +EXPORT_SYMBOL_GPL(tegra_read_ram_code); static const struct of_device_id apbmisc_match[] __initconst = { { .compatible = "nvidia,tegra20-apbmisc", }, From 245157a31e91aec7f5b621ed26c0a8370b1c8a64 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:39 +0300 Subject: [PATCH 08/38] soc/tegra: fuse: Add stub for tegra_sku_info Drivers that use tegra_sku_info and have COMPILE_TEST are failing to be build due to the missing stub for tegra_sku_info. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-4-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- include/soc/tegra/fuse.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index c702bd2911bc..78cbc787a4dc 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -56,7 +56,11 @@ u32 tegra_read_straps(void); u32 tegra_read_ram_code(void); int tegra_fuse_readl(unsigned long offset, u32 *value); +#ifdef CONFIG_ARCH_TEGRA extern struct tegra_sku_info tegra_sku_info; +#else +static struct tegra_sku_info tegra_sku_info __maybe_unused; +#endif struct device *tegra_soc_device_register(void); From e51a59f079c546b8b5c31604ad98e86b06ec93e9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:41 +0300 Subject: [PATCH 09/38] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Tegra20 External Memory Controller talks to DRAM chips and it needs to be reprogrammed when memory frequency changes. Tegra Memory Controller sits behind EMC and these controllers are tightly coupled. This patch adds the new phandle property which allows to properly express connection of EMC and MC hardware in a device-tree, it also put the Tegra20 EMC binding on par with Tegra30+ EMC bindings, which is handy to have. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-6-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 567cffd37f3f..1b0d4417aad8 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -12,6 +12,7 @@ Properties: irrespective of ram-code configuration. - interrupts : Should contain EMC General interrupt. - clocks : Should contain EMC clock. +- nvidia,memory-controller : Phandle of the Memory Controller node. Child device nodes describe the memory settings for different configurations and clock rates. @@ -24,6 +25,7 @@ Example: reg = <0x7000f400 0x400>; interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; + nvidia,memory-controller = <&mc>; } From 3ee81e021f2bd44b70312692b719995d398a84ee Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:42 +0300 Subject: [PATCH 10/38] dt-bindings: memory: tegra20: mc: Document new interconnect property Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-7-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra20-mc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt index e55328237df4..739b7c6f2e26 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt @@ -16,6 +16,8 @@ Required properties: IOMMU specifier needed to encode an address. GART supports only a single address space that is shared by all devices, therefore no additional information needed for the address encoding. +- #interconnect-cells : Should be 1. This cell represents memory client. + The assignments may be found in header file . Example: mc: memory-controller@7000f000 { @@ -27,6 +29,7 @@ Example: interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; video-codec@6001a000 { From 5e768b1fe46e6644cdbbbfa8c879c6cccb5639ba Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:43 +0300 Subject: [PATCH 11/38] dt-bindings: memory: tegra20: emc: Document new interconnect property External Memory Controller is interconnected with memory controller and with external memory. Document new interconnect property which turns EMC into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-8-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 1b0d4417aad8..82bc5b2ae7e5 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -13,6 +13,7 @@ Properties: - interrupts : Should contain EMC General interrupt. - clocks : Should contain EMC clock. - nvidia,memory-controller : Phandle of the Memory Controller node. +- #interconnect-cells : Should be 0. Child device nodes describe the memory settings for different configurations and clock rates. @@ -21,6 +22,7 @@ Example: memory-controller@7000f400 { #address-cells = < 1 >; #size-cells = < 0 >; + #interconnect-cells = <0>; compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x400>; interrupts = <0 78 0x04>; From 95e638e8b0b4bd0d51262bb7d01693039fc5ae48 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:44 +0300 Subject: [PATCH 12/38] dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator The SoC core voltage can't be changed without taking into account the clock rate of External Memory Controller. Document OPP table that will be used for dynamic voltage frequency scaling, taking into account EMC voltage requirement. Document optional core voltage regulator, which is optional because some boards may have a fixed core regulator and still frequency scaling may be desired to have. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-9-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/nvidia,tegra20-emc.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 82bc5b2ae7e5..67ac8d1297da 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -14,11 +14,25 @@ Properties: - clocks : Should contain EMC clock. - nvidia,memory-controller : Phandle of the Memory Controller node. - #interconnect-cells : Should be 0. +- operating-points-v2: See ../bindings/opp/opp.txt for details. + +Optional properties: +- core-supply: Phandle of voltage regulator of the SoC "core" power domain. Child device nodes describe the memory settings for different configurations and clock rates. Example: + opp_table: opp-table { + compatible = "operating-points-v2"; + + opp@36000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <36000000>; + }; + ... + }; + memory-controller@7000f400 { #address-cells = < 1 >; #size-cells = < 0 >; @@ -28,6 +42,8 @@ Example: interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; nvidia,memory-controller = <&mc>; + core-supply = <&core_vdd_reg>; + operating-points-v2 = <&opp_table>; } From ed7f6f2eaae850ee836bee05feb1df722c13efad Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:45 +0300 Subject: [PATCH 13/38] dt-bindings: memory: tegra30: mc: Document new interconnect property Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-10-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra30-mc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml index 84fd57bcf0dc..5436e6d420bc 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml @@ -57,6 +57,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -120,6 +123,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -135,6 +139,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-1 { nvidia,ram-code = <1>; From 6ec85c032aee0cde82b2c63a3e521132c97c4660 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:46 +0300 Subject: [PATCH 14/38] dt-bindings: memory: tegra30: emc: Document new interconnect property External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns External Memory Controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-11-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra30-emc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index 112bae2fcbbd..c243986db420 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -31,6 +31,9 @@ properties: interrupts: maxItems: 1 + "#interconnect-cells": + const: 0 + nvidia,memory-controller: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -214,6 +217,7 @@ required: - interrupts - clocks - nvidia,memory-controller + - "#interconnect-cells" additionalProperties: false @@ -227,6 +231,8 @@ examples: nvidia,memory-controller = <&mc>; + #interconnect-cells = <0>; + emc-timings-1 { nvidia,ram-code = <1>; From 48126d7884ab56c2352ae328d5fd42c7d2d7b125 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:47 +0300 Subject: [PATCH 15/38] dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator Document new OPP table and voltage regulator properties which are needed for supporting dynamic voltage-frequency scaling of the memory controller. Some boards may have a fixed core voltage regulator, hence it's optional because frequency scaling still may be desired. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-12-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/nvidia,tegra30-emc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index c243986db420..0a2e2c0d0fdd 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -39,6 +39,15 @@ properties: description: Phandle of the Memory Controller node. + core-supply: + description: + Phandle of voltage regulator of the SoC "core" power domain. + + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC speedo ID mask. + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -218,6 +227,7 @@ required: - clocks - nvidia,memory-controller - "#interconnect-cells" + - operating-points-v2 additionalProperties: false @@ -230,6 +240,8 @@ examples: clocks = <&tegra_car 57>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; #interconnect-cells = <0>; From cac2a3552c9ef3ee2ff9ec72794e1ab0a1f64012 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:48 +0300 Subject: [PATCH 16/38] dt-bindings: memory: tegra124: mc: Document new interconnect property Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-13-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 1 + .../bindings/memory-controllers/nvidia,tegra124-mc.yaml | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 278549f9e051..8ae3dae42d6e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -345,6 +345,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; external-memory-controller@7001b000 { diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index 84d0339505b1..7b18b4d11e0a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -40,6 +40,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -104,6 +107,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -119,6 +123,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-3 { nvidia,ram-code = <3>; From cf3b2deb459df1d1f3cdbd4d24b35e9f3506d92f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:49 +0300 Subject: [PATCH 17/38] dt-bindings: memory: tegra124: emc: Document new interconnect property External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns External Memory Controller into interconnect provider. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-14-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 8ae3dae42d6e..ac00832ceac1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -29,6 +29,9 @@ properties: items: - const: emc + "#interconnect-cells": + const: 0 + nvidia,memory-controller: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -327,6 +330,7 @@ required: - clocks - clock-names - nvidia,memory-controller + - "#interconnect-cells" additionalProperties: false @@ -356,6 +360,8 @@ examples: nvidia,memory-controller = <&mc>; + #interconnect-cells = <0>; + emc-timings-0 { nvidia,ram-code = <3>; From 881f68ed9d4e2d9f6e4247f2f01d9c457921e6c6 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:50 +0300 Subject: [PATCH 18/38] dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator Document new OPP table and voltage regulator properties which are needed for supporting dynamic voltage-frequency scaling of the memory controller. Some boards may have a fixed core voltage regulator, hence it's optional because frequency scaling still may be desired. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-15-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/nvidia,tegra124-emc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index ac00832ceac1..09bde65e1955 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -37,6 +37,15 @@ properties: description: phandle of the memory controller node + core-supply: + description: + Phandle of voltage regulator of the SoC "core" power domain. + + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC speedo ID mask. + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -331,6 +340,7 @@ required: - clock-names - nvidia,memory-controller - "#interconnect-cells" + - operating-points-v2 additionalProperties: false @@ -359,6 +369,8 @@ examples: clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; #interconnect-cells = <0>; From 254a42ac93900f92307a280daf4ccbd118c72255 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:51 +0300 Subject: [PATCH 19/38] dt-bindings: tegra30-actmon: Document OPP and interconnect properties Document EMC DFS OPP table and interconnect paths that will be used for scaling of system's memory bandwidth based on memory utilization statistics. Previously ACTMON was supposed to drive EMC clock rate directly, but now it should do it using interconnect framework in order to support shared voltage scaling in addition to the frequency scaling. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-16-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../arm/tegra/nvidia,tegra30-actmon.txt | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt index ea670a5d7ee3..897eedfa2bc8 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt @@ -18,8 +18,30 @@ clock-names. See ../../clock/clock-bindings.txt for details. ../../reset/reset.txt for details. - reset-names: Must include the following entries: - actmon +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- interconnects: Should contain entries for memory clients sitting on + MC->EMC memory interconnect path. +- interconnect-names: Should include name of the interconnect path for each + interconnect entry. Consult TRM documentation for + information about available memory clients, see MEMORY + CONTROLLER section. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: bitfield indicating SoC speedo ID mask +- opp-peak-kBps: peak bandwidth of the memory channel Example: + dfs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp@12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <51000>; + }; + ... + }; + actmon@6000c800 { compatible = "nvidia,tegra124-actmon"; reg = <0x0 0x6000c800 0x0 0x400>; @@ -29,4 +51,7 @@ Example: clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu"; }; From c553bb54a486eab2b0d3671db4b985c8d1ba51e9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:52 +0300 Subject: [PATCH 20/38] dt-bindings: host1x: Document new interconnect properties Most of Host1x devices have at least one memory client. These clients are directly connected to the memory controller. The new interconnect properties represent the memory client's connection to the memory controller. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-17-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../display/tegra/nvidia,tegra20-host1x.txt | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index ac63ae4a3861..34d993338453 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,10 @@ Required properties: - reset-names: Must include the following entries: - host1x +Each host1x client module having to perform DMA through the Memory Controller +should have the interconnect endpoints set to the Memory Client and External +Memory respectively. + The host1x top-level node defines a number of children, each representing one of the following host1x client modules: @@ -36,6 +40,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - mpe + Optional properties: + - interconnects: Must contain entry for the MPE memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - vi: video input Required properties: @@ -113,6 +123,12 @@ of the following host1x client modules: Required properties: - remote-endpoint: phandle to vi port 'endpoint' node. + Optional properties: + - interconnects: Must contain entry for the VI memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - epp: encoder pre-processor Required properties: @@ -126,6 +142,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - epp + Optional properties: + - interconnects: Must contain entry for the EPP memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - isp: image signal processor Required properties: @@ -139,6 +161,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - isp + Optional properties: + - interconnects: Must contain entry for the ISP memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - gr2d: 2D graphics engine Required properties: @@ -152,6 +180,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - 2d + Optional properties: + - interconnects: Must contain entry for the GR2D memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - gr3d: 3D graphics engine Required properties: @@ -170,6 +204,12 @@ of the following host1x client modules: - 3d - 3d2 (Only required on SoCs with two 3D clocks) + Optional properties: + - interconnects: Must contain entry for the GR3D memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - dc: display controller Required properties: @@ -197,6 +237,10 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - interconnects: Must contain entry for the DC memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. - hdmi: High Definition Multimedia Interface @@ -345,6 +389,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - vic + Optional properties: + - interconnects: Must contain entry for the VIC memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + Example: / { @@ -498,6 +548,15 @@ Example: resets = <&tegra_car 27>; reset-names = "dc"; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -513,6 +572,15 @@ Example: resets = <&tegra_car 26>; reset-names = "dc"; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; From 6c6bd2075f01f8c8ae4bc803ba5cd23a3d3db533 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:04 +0300 Subject: [PATCH 21/38] memory: tegra: Add and use devm_tegra_memory_controller_get() Multiple Tegra drivers need to retrieve Memory Controller and there is duplication of the retrieval code among the drivers. Add new devm_tegra_memory_controller_get() helper to remove the code's duplication and to fix put_device() which was missed in the duplicated code. Make EMC drivers to use the new helper. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201104164923.21238-29-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 48 ++++++++++++++++++++++++ drivers/memory/tegra/tegra124-emc.c | 18 ++------- drivers/memory/tegra/tegra210-emc-core.c | 39 +++++-------------- drivers/memory/tegra/tegra30-emc.c | 18 ++------- include/soc/tegra/mc.h | 10 +++++ 5 files changed, 74 insertions(+), 59 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index ec8403557ed4..a72cdcafc933 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -42,6 +42,54 @@ static const struct of_device_id tegra_mc_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); +static void tegra_mc_devm_action_put_device(void *data) +{ + struct tegra_mc *mc = data; + + put_device(mc->dev); +} + +/** + * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle + * @dev: device pointer for the consumer device + * + * This function will search for the Memory Controller node in a device-tree + * and retrieve the Memory Controller handle. + * + * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc. + */ +struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev) +{ + struct platform_device *pdev; + struct device_node *np; + struct tegra_mc *mc; + int err; + + np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0); + if (!np) + return ERR_PTR(-ENOENT); + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return ERR_PTR(-ENODEV); + + mc = platform_get_drvdata(pdev); + if (!mc) { + put_device(&pdev->dev); + return ERR_PTR(-EPROBE_DEFER); + } + + err = devm_add_action(dev, tegra_mc_devm_action_put_device, mc); + if (err) { + put_device(mc->dev); + return ERR_PTR(err); + } + + return mc; +} +EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get); + static int tegra_mc_block_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 76ace42a688a..35dbceb7f841 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -1177,7 +1177,6 @@ static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc) static int tegra_emc_probe(struct platform_device *pdev) { - struct platform_device *mc; struct device_node *np; struct tegra_emc *emc; struct resource *res; @@ -1195,20 +1194,9 @@ static int tegra_emc_probe(struct platform_device *pdev) if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); - if (!np) { - dev_err(&pdev->dev, "could not get memory controller\n"); - return -ENOENT; - } - - mc = of_find_device_by_node(np); - of_node_put(np); - if (!mc) - return -ENOENT; - - emc->mc = platform_get_drvdata(mc); - if (!emc->mc) - return -EPROBE_DEFER; + emc->mc = devm_tegra_memory_controller_get(&pdev->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); ram_code = tegra_read_ram_code(); diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c index cdd663ba4733..5f224796e32e 100644 --- a/drivers/memory/tegra/tegra210-emc-core.c +++ b/drivers/memory/tegra/tegra210-emc-core.c @@ -1828,7 +1828,6 @@ static int tegra210_emc_probe(struct platform_device *pdev) { struct thermal_cooling_device *cd; unsigned long current_rate; - struct platform_device *mc; struct tegra210_emc *emc; struct device_node *np; unsigned int i; @@ -1846,35 +1845,19 @@ static int tegra210_emc_probe(struct platform_device *pdev) spin_lock_init(&emc->lock); emc->dev = &pdev->dev; - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); - if (!np) { - dev_err(&pdev->dev, "could not get memory controller\n"); - return -ENOENT; - } - - mc = of_find_device_by_node(np); - of_node_put(np); - if (!mc) - return -ENOENT; - - emc->mc = platform_get_drvdata(mc); - if (!emc->mc) { - put_device(&mc->dev); - return -EPROBE_DEFER; - } + emc->mc = devm_tegra_memory_controller_get(&pdev->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); emc->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(emc->regs)) { - err = PTR_ERR(emc->regs); - goto put_mc; - } + if (IS_ERR(emc->regs)) + return PTR_ERR(emc->regs); for (i = 0; i < 2; i++) { emc->channel[i] = devm_platform_ioremap_resource(pdev, 1 + i); - if (IS_ERR(emc->channel[i])) { - err = PTR_ERR(emc->channel[i]); - goto put_mc; - } + if (IS_ERR(emc->channel[i])) + return PTR_ERR(emc->channel[i]); + } tegra210_emc_detect(emc); @@ -1884,7 +1867,7 @@ static int tegra210_emc_probe(struct platform_device *pdev) err = of_reserved_mem_device_init_by_name(emc->dev, np, "nominal"); if (err < 0) { dev_err(emc->dev, "failed to get nominal EMC table: %d\n", err); - goto put_mc; + return err; } err = of_reserved_mem_device_init_by_name(emc->dev, np, "derated"); @@ -2015,8 +1998,7 @@ detach: tegra210_clk_emc_detach(emc->clk); release: of_reserved_mem_device_release(emc->dev); -put_mc: - put_device(emc->mc->dev); + return err; } @@ -2027,7 +2009,6 @@ static int tegra210_emc_remove(struct platform_device *pdev) debugfs_remove_recursive(emc->debugfs.root); tegra210_clk_emc_detach(emc->clk); of_reserved_mem_device_release(emc->dev); - put_device(emc->mc->dev); return 0; } diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 055af0e08a2e..c58cf31cb27b 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1258,7 +1258,6 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) static int tegra_emc_probe(struct platform_device *pdev) { - struct platform_device *mc; struct device_node *np; struct tegra_emc *emc; int err; @@ -1269,17 +1268,6 @@ static int tegra_emc_probe(struct platform_device *pdev) return -ENODEV; } - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); - if (!np) { - dev_err(&pdev->dev, "could not get memory controller node\n"); - return -ENOENT; - } - - mc = of_find_device_by_node(np); - of_node_put(np); - if (!mc) - return -ENOENT; - np = emc_find_node_by_ram_code(&pdev->dev); if (!np) return -EINVAL; @@ -1290,9 +1278,9 @@ static int tegra_emc_probe(struct platform_device *pdev) return -ENOMEM; } - emc->mc = platform_get_drvdata(mc); - if (!emc->mc) - return -EPROBE_DEFER; + emc->mc = devm_tegra_memory_controller_get(&pdev->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1238e35653d1..d9395af98143 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -184,4 +184,14 @@ struct tegra_mc { int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate); unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc); +#ifdef CONFIG_TEGRA_MC +struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev); +#else +static inline struct tegra_mc * +devm_tegra_memory_controller_get(struct device *dev) +{ + ERR_PTR(-ENODEV); +} +#endif + #endif /* __SOC_TEGRA_MC_H__ */ From 4e84d0a6e1206fda47395b5d3af1453e013d7b38 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:05 +0300 Subject: [PATCH 22/38] memory: tegra: Use devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() helper which makes code a bit cleaner. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201104164923.21238-30-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra124-emc.c | 4 +--- drivers/memory/tegra/tegra20-emc.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 35dbceb7f841..ee8ee39e98ed 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -1179,7 +1179,6 @@ static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; struct tegra_emc *emc; - struct resource *res; u32 ram_code; int err; @@ -1189,8 +1188,7 @@ static int tegra_emc_probe(struct platform_device *pdev) emc->dev = &pdev->dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - emc->regs = devm_ioremap_resource(&pdev->dev, res); + emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 027f46287dbf..5ba4e495bfc3 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -654,7 +654,6 @@ static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; struct tegra_emc *emc; - struct resource *res; int irq, err; /* driver has nothing to do in a case of memory timing absence */ @@ -689,8 +688,7 @@ static int tegra_emc_probe(struct platform_device *pdev) if (err) return err; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - emc->regs = devm_ioremap_resource(&pdev->dev, res); + emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); From 162641a6e200e935cd39b26737f3ec0b5ea856fb Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:06 +0300 Subject: [PATCH 23/38] memory: tegra: Remove superfluous error messages around platform_get_irq() The platform_get_irq() prints error message telling that interrupt is missing, hence there is no need to duplicated that message in the drivers. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-31-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 4 +--- drivers/memory/tegra/tegra20-emc.c | 1 - drivers/memory/tegra/tegra30-emc.c | 5 ++--- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index a72cdcafc933..998f9148ecb8 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -707,10 +707,8 @@ static int tegra_mc_probe(struct platform_device *pdev) } mc->irq = platform_get_irq(pdev, 0); - if (mc->irq < 0) { - dev_err(&pdev->dev, "interrupt not specified\n"); + if (mc->irq < 0) return mc->irq; - } WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 5ba4e495bfc3..c9fe58a724ee 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -665,7 +665,6 @@ static int tegra_emc_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) { - dev_err(&pdev->dev, "interrupt not specified\n"); dev_err(&pdev->dev, "please update your device tree\n"); return irq; } diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index c58cf31cb27b..1be28e28ec34 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1299,10 +1299,9 @@ static int tegra_emc_probe(struct platform_device *pdev) return err; err = platform_get_irq(pdev, 0); - if (err < 0) { - dev_err(&pdev->dev, "interrupt not specified: %d\n", err); + if (err < 0) return err; - } + emc->irq = err; err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0, From d5ecac0afa30811901eb401067f196e688aeb73e Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:07 +0300 Subject: [PATCH 24/38] memory: tegra: Add missing latency allowness entry for Page Table Cache Add missing PTC memory client latency allowness entry to the Tegra MC drivers. This prevents erroneous clearing of MC_INTSTATUS 0x0 register during of the LA programming in tegra_mc_setup_latency_allowance() due to the missing entry. Note that this patch doesn't fix any known problems. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-32-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra114.c | 6 ++++++ drivers/memory/tegra/tegra124.c | 6 ++++++ drivers/memory/tegra/tegra30.c | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c index 48ef01c3ff90..ed376ba2d2fe 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -15,6 +15,12 @@ static const struct tegra_mc_client tegra114_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index 0cede24479bf..e2389573d3c0 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -15,6 +15,12 @@ static const struct tegra_mc_client tegra124_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index fcdd812eed80..b1990b4133d8 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -36,6 +36,12 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", From 06f079816d4c4e43d4128f394ae249934a32dffd Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:08 +0300 Subject: [PATCH 25/38] memory: tegra-mc: Add interconnect framework Add common SoC-agnostic ICC framework which turns Tegra Memory Controller into a memory interconnection provider. This allows us to use interconnect API for tuning of memory configurations. Signed-off-by: Dmitry Osipenko Tested-by: Peter Geis Tested-by: Nicolas Chauvet Link: https://lore.kernel.org/r/20201104164923.21238-33-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/mc.c | 100 +++++++++++++++++++++++++++++++++++ drivers/memory/tegra/mc.h | 22 ++++++++ include/soc/tegra/mc.h | 17 ++++++ 4 files changed, 140 insertions(+) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 9f0a96bf9ccc..b38e5255effe 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -3,6 +3,7 @@ config TEGRA_MC bool "NVIDIA Tegra Memory Controller support" default y depends on ARCH_TEGRA + select INTERCONNECT help This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 998f9148ecb8..a7e6a8e4c95a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -639,6 +639,101 @@ static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) return IRQ_HANDLED; } +/* + * Memory Controller (MC) has few Memory Clients that are issuing memory + * bandwidth allocation requests to the MC interconnect provider. The MC + * provider aggregates the requests and then sends the aggregated request + * up to the External Memory Controller (EMC) interconnect provider which + * re-configures hardware interface to External Memory (EMEM) in accordance + * to the required bandwidth. Each MC interconnect node represents an + * individual Memory Client. + * + * Memory interconnect topology: + * + * +----+ + * +--------+ | | + * | TEXSRD +--->+ | + * +--------+ | | + * | | +-----+ +------+ + * ... | MC +--->+ EMC +--->+ EMEM | + * | | +-----+ +------+ + * +--------+ | | + * | DISP.. +--->+ | + * +--------+ | | + * +----+ + */ +static int tegra_mc_interconnect_setup(struct tegra_mc *mc) +{ + struct icc_node *node; + unsigned int i; + int err; + + /* older device-trees don't have interconnect properties */ + if (!device_property_present(mc->dev, "#interconnect-cells") || + !mc->soc->icc_ops) + return 0; + + mc->provider.dev = mc->dev; + mc->provider.data = &mc->provider; + mc->provider.set = mc->soc->icc_ops->set; + mc->provider.aggregate = mc->soc->icc_ops->aggregate; + mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; + + err = icc_provider_add(&mc->provider); + if (err) + return err; + + /* create Memory Controller node */ + node = icc_node_create(TEGRA_ICC_MC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "Memory Controller"; + icc_node_add(node, &mc->provider); + + /* link Memory Controller to External Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_EMC); + if (err) + goto remove_nodes; + + for (i = 0; i < mc->soc->num_clients; i++) { + /* create MC client node */ + node = icc_node_create(mc->soc->clients[i].id); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = mc->soc->clients[i].name; + icc_node_add(node, &mc->provider); + + /* link Memory Client to Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_MC); + if (err) + goto remove_nodes; + } + + /* + * MC driver is registered too early, so early that generic driver + * syncing doesn't work for the MC. But it doesn't really matter + * since syncing works for the EMC drivers, hence we can sync the + * MC driver by ourselves and then EMC will complete syncing of + * the whole ICC state. + */ + icc_sync_state(mc->dev); + + return 0; + +remove_nodes: + icc_nodes_remove(&mc->provider); +del_provider: + icc_provider_del(&mc->provider); + + return err; +} + static int tegra_mc_probe(struct platform_device *pdev) { struct resource *res; @@ -727,6 +822,11 @@ static int tegra_mc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); + err = tegra_mc_interconnect_setup(mc); + if (err < 0) + dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", + err); + if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); if (IS_ERR(mc->smmu)) { diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index afa3ba45c9e6..33e40d600592 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -78,6 +78,20 @@ #define MC_TIMING_UPDATE BIT(0) +static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) +{ + val = val * percents; + do_div(val, 100); + + return min_t(u64, val, U32_MAX); +} + +static inline struct tegra_mc * +icc_provider_to_tegra_mc(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_mc, provider); +} + static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset) { return readl_relaxed(mc->regs + offset); @@ -115,4 +129,12 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +/* + * These IDs are for internal use of Tegra ICC drivers. The ID numbers are + * chosen such that they don't conflict with the device-tree ICC node IDs. + */ +#define TEGRA_ICC_MC 1000 +#define TEGRA_ICC_EMC 1001 +#define TEGRA_ICC_EMEM 1002 + #endif /* MEMORY_TEGRA_MC_H */ diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index d9395af98143..43876216de34 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -6,7 +6,9 @@ #ifndef __SOC_TEGRA_MC_H__ #define __SOC_TEGRA_MC_H__ +#include #include +#include #include #include @@ -141,6 +143,17 @@ struct tegra_mc_reset_ops { const struct tegra_mc_reset *rst); }; +#define TEGRA_MC_ICC_TAG_DEFAULT 0 +#define TEGRA_MC_ICC_TAG_ISO BIT(0) + +struct tegra_mc_icc_ops { + int (*set)(struct icc_node *src, struct icc_node *dst); + int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak); + struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec, + void *data); +}; + struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -160,6 +173,8 @@ struct tegra_mc_soc { const struct tegra_mc_reset_ops *reset_ops; const struct tegra_mc_reset *resets; unsigned int num_resets; + + const struct tegra_mc_icc_ops *icc_ops; }; struct tegra_mc { @@ -178,6 +193,8 @@ struct tegra_mc { struct reset_controller_dev reset; + struct icc_provider provider; + spinlock_t lock; }; From 0260979b018faaf90ff5a7bb04ac3f38e9dee6e3 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:09 +0300 Subject: [PATCH 26/38] memory: tegra20-emc: Make driver modular Add modularization support to the Tegra20 EMC driver, which now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201104164923.21238-34-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra20-emc.c | 17 ++++++++++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index b38e5255effe..ff426747cd7d 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -9,7 +9,7 @@ config TEGRA_MC NVIDIA Tegra SoCs. config TEGRA20_EMC - bool "NVIDIA Tegra20 External Memory Controller driver" + tristate "NVIDIA Tegra20 External Memory Controller driver" default y depends on ARCH_TEGRA_2x_SOC help diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index c9fe58a724ee..88619e3ec435 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -721,6 +721,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; unset_cb: @@ -733,6 +740,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra20-emc", }, {}, }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct platform_driver tegra_emc_driver = { .probe = tegra_emc_probe, @@ -742,9 +750,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int __init tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Dmitry Osipenko "); +MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver"); +MODULE_LICENSE("GPL v2"); From fa4794ff8fb4b324ae5b9f089312bcd4ce4ff6ed Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:10 +0300 Subject: [PATCH 27/38] memory: tegra20-emc: Continue probing if timings are missing in device-tree EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-35-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra20-emc.c | 34 ++++++++++++++---------------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 88619e3ec435..a49658d217a7 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -383,6 +383,11 @@ tegra_emc_find_node_by_ram_code(struct device *dev) u32 value, ram_code; int err; + if (of_get_child_count(dev->of_node) == 0) { + dev_info(dev, "device-tree doesn't have memory timings\n"); + return NULL; + } + if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) return of_node_get(dev->of_node); @@ -451,6 +456,9 @@ static long emc_round_rate(unsigned long rate, struct tegra_emc *emc = arg; unsigned int i; + if (!emc->num_timings) + return clk_get_rate(emc->clk); + min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); for (i = 0; i < emc->num_timings; i++) { @@ -656,36 +664,26 @@ static int tegra_emc_probe(struct platform_device *pdev) struct tegra_emc *emc; int irq, err; - /* driver has nothing to do in a case of memory timing absence */ - if (of_get_child_count(pdev->dev.of_node) == 0) { - dev_info(&pdev->dev, - "EMC device tree node doesn't have memory timings\n"); - return 0; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "please update your device tree\n"); return irq; } - np = tegra_emc_find_node_by_ram_code(&pdev->dev); - if (!np) - return -EINVAL; - emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); - if (!emc) { - of_node_put(np); + if (!emc) return -ENOMEM; - } emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; emc->dev = &pdev->dev; - err = tegra_emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) - return err; + np = tegra_emc_find_node_by_ram_code(&pdev->dev); + if (np) { + err = tegra_emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + } emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) From d5ef16ba5fbe128873a55441d85ccde77f63c129 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:11 +0300 Subject: [PATCH 28/38] memory: tegra20: Support interconnect framework Now Internal and External Memory Controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-36-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 3 +- drivers/memory/tegra/tegra20-emc.c | 310 ++++++++++++++++++++++++++++- drivers/memory/tegra/tegra20.c | 77 +++++++ 3 files changed, 386 insertions(+), 4 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index ff426747cd7d..ac3dfe155505 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -11,7 +11,8 @@ config TEGRA_MC config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y - depends on ARCH_TEGRA_2x_SOC + depends on TEGRA_MC && ARCH_TEGRA_2x_SOC + select PM_OPP help This driver is for the External Memory Controller (EMC) found on Tegra20 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index a49658d217a7..5e10aa97809f 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -9,18 +9,25 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include +#include +#include #include #include +#include #include +#include "mc.h" + #define EMC_INTSTATUS 0x000 #define EMC_INTMASK 0x004 #define EMC_DBG 0x008 @@ -62,6 +69,11 @@ #define EMC_ODT_READ 0x0b4 #define EMC_FBIO_CFG5 0x104 #define EMC_FBIO_CFG6 0x114 +#define EMC_STAT_CONTROL 0x160 +#define EMC_STAT_LLMC_CONTROL 0x178 +#define EMC_STAT_PWR_CLOCK_LIMIT 0x198 +#define EMC_STAT_PWR_CLOCKS 0x19c +#define EMC_STAT_PWR_COUNT 0x1a0 #define EMC_AUTO_CAL_INTERVAL 0x2a8 #define EMC_CFG_2 0x2b8 #define EMC_CFG_DIG_DLL 0x2bc @@ -88,6 +100,8 @@ #define EMC_DBG_READ_DQM_CTRL BIT(9) #define EMC_DBG_CFG_PRIORITY BIT(24) +#define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4) + static const u16 emc_timing_registers[] = { EMC_RC, EMC_RFC, @@ -142,11 +156,25 @@ struct emc_timing { u32 data[ARRAY_SIZE(emc_timing_registers)]; }; +enum emc_rate_request_type { + EMC_RATE_DEBUG, + EMC_RATE_ICC, + EMC_RATE_TYPE_MAX, +}; + +struct emc_rate_request { + unsigned long min_rate; + unsigned long max_rate; +}; + struct tegra_emc { struct device *dev; + struct tegra_mc *mc; + struct icc_provider provider; struct notifier_block clk_nb; struct clk *clk; void __iomem *regs; + unsigned int dram_bus_width; struct emc_timing *timings; unsigned int num_timings; @@ -156,6 +184,15 @@ struct tegra_emc { unsigned long min_rate; unsigned long max_rate; } debugfs; + + /* + * There are multiple sources in the EMC driver which could request + * a min/max clock rate, these rates are contained in this array. + */ + struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; + + /* protect shared rate-change code path */ + struct mutex rate_lock; }; static irqreturn_t tegra_emc_isr(int irq, void *data) @@ -413,7 +450,7 @@ tegra_emc_find_node_by_ram_code(struct device *dev) static int emc_setup_hw(struct tegra_emc *emc) { u32 intmask = EMC_REFRESH_OVERFLOW_INT; - u32 emc_cfg, emc_dbg; + u32 emc_cfg, emc_dbg, emc_fbio; emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); @@ -444,6 +481,15 @@ static int emc_setup_hw(struct tegra_emc *emc) emc_dbg &= ~EMC_DBG_FORCE_UPDATE; writel_relaxed(emc_dbg, emc->regs + EMC_DBG); + emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5); + + if (emc_fbio & EMC_FBIO_CFG5_DRAM_WIDTH_X16) + emc->dram_bus_width = 16; + else + emc->dram_bus_width = 32; + + dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); + return 0; } @@ -488,6 +534,83 @@ static long emc_round_rate(unsigned long rate, return timing->rate; } +static void tegra_emc_rate_requests_init(struct tegra_emc *emc) +{ + unsigned int i; + + for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { + emc->requested_rate[i].min_rate = 0; + emc->requested_rate[i].max_rate = ULONG_MAX; + } +} + +static int emc_request_rate(struct tegra_emc *emc, + unsigned long new_min_rate, + unsigned long new_max_rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = emc->requested_rate; + unsigned long min_rate = 0, max_rate = ULONG_MAX; + unsigned int i; + int err; + + /* select minimum and maximum rates among the requested rates */ + for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { + if (i == type) { + min_rate = max(new_min_rate, min_rate); + max_rate = min(new_max_rate, max_rate); + } else { + min_rate = max(req->min_rate, min_rate); + max_rate = min(req->max_rate, max_rate); + } + } + + if (min_rate > max_rate) { + dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", + __func__, type, min_rate, max_rate); + return -ERANGE; + } + + /* + * EMC rate-changes should go via OPP API because it manages voltage + * changes. + */ + err = dev_pm_opp_set_rate(emc->dev, min_rate); + if (err) + return err; + + emc->requested_rate[type].min_rate = new_min_rate; + emc->requested_rate[type].max_rate = new_max_rate; + + return 0; +} + +static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, rate, req->max_rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + +static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, req->min_rate, rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + /* * debugfs interface * @@ -571,7 +694,7 @@ static int tegra_emc_debug_min_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_min_rate(emc->clk, rate); + err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -601,7 +724,7 @@ static int tegra_emc_debug_max_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_max_rate(emc->clk, rate); + err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -658,6 +781,177 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node_data * +emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node_data *ndata; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id != TEGRA_ICC_EMEM) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + /* + * SRC and DST nodes should have matching TAG in order to have + * it set by default for a requested path. + */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + ndata->node = node; + + return ndata; + } + + return ERR_PTR(-EPROBE_DEFER); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); + unsigned long long rate = max(avg_bw, peak_bw); + unsigned int dram_data_bus_width_bytes; + int err; + + /* + * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data + * is sampled on both clock edges. This means that EMC clock rate + * equals to the peak data-rate. + */ + dram_data_bus_width_bytes = emc->dram_bus_width / 8; + do_div(rate, dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); + if (err) + return err; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + const struct tegra_mc_soc *soc; + struct icc_node *node; + int err; + + emc->mc = devm_tegra_memory_controller_get(emc->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); + + soc = emc->mc->soc; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.aggregate = soc->icc_ops->aggregate; + emc->provider.xlate_extended = emc_of_icc_xlate_extended; + + err = icc_provider_add(&emc->provider); + if (err) + goto err_msg; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +del_provider: + icc_provider_del(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + +static int tegra_emc_opp_table_init(struct tegra_emc *emc) +{ + struct opp_table *opp_table; + const char *rname = "core"; + int err; + + /* + * Legacy device-trees don't have OPP table and EMC driver isn't + * useful in this case. + */ + if (!device_property_present(emc->dev, "operating-points-v2")) { + dev_err(emc->dev, + "OPP table not found, please update your device tree\n"); + return -ENODEV; + } + + /* voltage scaling is optional */ + if (device_property_present(emc->dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(emc->dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(emc->dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + err = dev_pm_opp_of_add_table(emc->dev); + if (err) { + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + goto put_table; + } + + dev_info(emc->dev, "current clock rate %lu MHz\n", + clk_get_rate(emc->clk) / 1000000); + + /* first dummy rate-set initializes voltage state */ + err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); + if (err) { + dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); + goto remove_table; + } + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(emc->dev); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -674,6 +968,7 @@ static int tegra_emc_probe(struct platform_device *pdev) if (!emc) return -ENOMEM; + mutex_init(&emc->rate_lock); emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; emc->dev = &pdev->dev; @@ -716,8 +1011,14 @@ static int tegra_emc_probe(struct platform_device *pdev) goto unset_cb; } + err = tegra_emc_opp_table_init(emc); + if (err) + goto unreg_notifier; + platform_set_drvdata(pdev, emc); + tegra_emc_rate_requests_init(emc); tegra_emc_debugfs_init(emc); + tegra_emc_interconnect_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some @@ -728,6 +1029,8 @@ static int tegra_emc_probe(struct platform_device *pdev) return 0; +unreg_notifier: + clk_notifier_unregister(emc->clk, &emc->clk_nb); unset_cb: tegra20_clk_set_emc_round_callback(NULL, NULL); @@ -746,6 +1049,7 @@ static struct platform_driver tegra_emc_driver = { .name = "tegra20-emc", .of_match_table = tegra_emc_of_match, .suppress_bind_attrs = true, + .sync_state = icc_sync_state, }, }; module_platform_driver(tegra_emc_driver); diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index a8098bff91d9..29ecf02805a0 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -3,6 +3,10 @@ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. */ +#include +#include +#include + #include #include "mc.h" @@ -280,6 +284,78 @@ static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = { .reset_status = tegra20_mc_reset_status, }; +static int tegra20_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + /* + * It should be possible to tune arbitration knobs here, but the + * default values are known to work well on all devices. Hence + * nothing to do here so far. + */ + return 0; +} + +static int tegra20_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + /* + * ISO clients need to reserve extra bandwidth up-front because + * there could be high bandwidth pressure during initial filling + * of the client's FIFO buffers. Secondly, we need to take into + * account impurities of the memory subsystem. + */ + if (tag & TEGRA_MC_ICC_TAG_ISO) + peak_bw = tegra_mc_scale_percents(peak_bw, 300); + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static struct icc_node_data * +tegra20_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(data); + unsigned int i, idx = spec->args[0]; + struct icc_node_data *ndata; + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id != idx) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + ndata->node = node; + + /* these clients are isochronous by default */ + if (strstarts(node->name, "display") || + strstarts(node->name, "vi")) + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + else + ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT; + + return ndata; + } + + for (i = 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id == idx) + return ERR_PTR(-EPROBE_DEFER); + } + + dev_err(mc->dev, "invalid ICC client ID %u\n", idx); + + return ERR_PTR(-EINVAL); +} + +static const struct tegra_mc_icc_ops tegra20_mc_icc_ops = { + .xlate_extended = tegra20_mc_of_icc_xlate_extended, + .aggregate = tegra20_mc_icc_aggreate, + .set = tegra20_mc_icc_set, +}; + const struct tegra_mc_soc tegra20_mc_soc = { .clients = tegra20_mc_clients, .num_clients = ARRAY_SIZE(tegra20_mc_clients), @@ -290,4 +366,5 @@ const struct tegra_mc_soc tegra20_mc_soc = { .reset_ops = &tegra20_mc_reset_ops, .resets = tegra20_mc_resets, .num_resets = ARRAY_SIZE(tegra20_mc_resets), + .icc_ops = &tegra20_mc_icc_ops, }; From 3a0b6b5abfddd0baf0a053aec7e8be59cf33b659 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:31 +0300 Subject: [PATCH 29/38] memory: tegra: Correct stub of devm_tegra_memory_controller_get() Correct typo in a stub of devm_tegra_memory_controller_get() to fix a non-ARM kernel compile-testing. Reported-by: Stephen Rothwell Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-2-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- include/soc/tegra/mc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 43876216de34..d731407e23bb 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -207,7 +207,7 @@ struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev); static inline struct tegra_mc * devm_tegra_memory_controller_get(struct device *dev) { - ERR_PTR(-ENODEV); + return ERR_PTR(-ENODEV); } #endif From de47653bd4dd3c1bf38c9983cf19556cab4c4211 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:32 +0300 Subject: [PATCH 30/38] memory: tegra20-emc: Use dev_pm_opp_set_clkname() The dev_pm_opp_get_opp_table() shouldn't be used by drivers, use dev_pm_opp_set_clkname() instead. Suggested-by: Viresh Kumar Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-3-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra20-emc.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 5e10aa97809f..bb3f315c9587 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -902,7 +902,7 @@ err_msg: static int tegra_emc_opp_table_init(struct tegra_emc *emc) { - struct opp_table *opp_table; + struct opp_table *reg_opp_table = NULL, *clk_opp_table; const char *rname = "core"; int err; @@ -917,19 +917,24 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) } /* voltage scaling is optional */ - if (device_property_present(emc->dev, "core-supply")) - opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); - else - opp_table = dev_pm_opp_get_opp_table(emc->dev); + if (device_property_present(emc->dev, "core-supply")) { + reg_opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); + if (IS_ERR(reg_opp_table)) + return dev_err_probe(emc->dev, PTR_ERR(reg_opp_table), + "failed to set OPP regulator\n"); + } - if (IS_ERR(opp_table)) - return dev_err_probe(emc->dev, PTR_ERR(opp_table), - "failed to prepare OPP table\n"); + clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL); + err = PTR_ERR_OR_ZERO(clk_opp_table); + if (err) { + dev_err(emc->dev, "failed to set OPP clk: %d\n", err); + goto put_reg_table; + } err = dev_pm_opp_of_add_table(emc->dev); if (err) { dev_err(emc->dev, "failed to add OPP table: %d\n", err); - goto put_table; + goto put_clk_table; } dev_info(emc->dev, "current clock rate %lu MHz\n", @@ -946,8 +951,11 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) remove_table: dev_pm_opp_of_remove_table(emc->dev); -put_table: - dev_pm_opp_put_regulators(opp_table); +put_clk_table: + dev_pm_opp_put_clkname(clk_opp_table); +put_reg_table: + if (reg_opp_table) + dev_pm_opp_put_regulators(reg_opp_table); return err; } From cba3902b0c3df42969231358a5e8b3d40212b7ad Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:33 +0300 Subject: [PATCH 31/38] memory: tegra20-emc: Factor out clk initialization Factor out clk initialization and make it resource-managed. This makes easier to follow code and will help to make further changes cleaner. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-4-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra20-emc.c | 70 ++++++++++++++++++++---------- 1 file changed, 47 insertions(+), 23 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index bb3f315c9587..d01b556a6d06 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -960,6 +960,49 @@ put_reg_table: return err; } +static void devm_tegra_emc_unset_callback(void *data) +{ + tegra20_clk_set_emc_round_callback(NULL, NULL); +} + +static void devm_tegra_emc_unreg_clk_notifier(void *data) +{ + struct tegra_emc *emc = data; + + clk_notifier_unregister(emc->clk, &emc->clk_nb); +} + +static int tegra_emc_init_clk(struct tegra_emc *emc) +{ + int err; + + tegra20_clk_set_emc_round_callback(emc_round_rate, emc); + + err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, + NULL); + if (err) + return err; + + emc->clk = devm_clk_get(emc->dev, NULL); + if (IS_ERR(emc->clk)) { + dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk); + return PTR_ERR(emc->clk); + } + + err = clk_notifier_register(emc->clk, &emc->clk_nb); + if (err) { + dev_err(emc->dev, "failed to register clk notifier: %d\n", err); + return err; + } + + err = devm_add_action_or_reset(emc->dev, + devm_tegra_emc_unreg_clk_notifier, emc); + if (err) + return err; + + return 0; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -1003,25 +1046,13 @@ static int tegra_emc_probe(struct platform_device *pdev) return err; } - tegra20_clk_set_emc_round_callback(emc_round_rate, emc); - - emc->clk = devm_clk_get(&pdev->dev, "emc"); - if (IS_ERR(emc->clk)) { - err = PTR_ERR(emc->clk); - dev_err(&pdev->dev, "failed to get emc clock: %d\n", err); - goto unset_cb; - } - - err = clk_notifier_register(emc->clk, &emc->clk_nb); - if (err) { - dev_err(&pdev->dev, "failed to register clk notifier: %d\n", - err); - goto unset_cb; - } + err = tegra_emc_init_clk(emc); + if (err) + return err; err = tegra_emc_opp_table_init(emc); if (err) - goto unreg_notifier; + return err; platform_set_drvdata(pdev, emc); tegra_emc_rate_requests_init(emc); @@ -1036,13 +1067,6 @@ static int tegra_emc_probe(struct platform_device *pdev) try_module_get(THIS_MODULE); return 0; - -unreg_notifier: - clk_notifier_unregister(emc->clk, &emc->clk_nb); -unset_cb: - tegra20_clk_set_emc_round_callback(NULL, NULL); - - return err; } static const struct of_device_id tegra_emc_of_match[] = { From e09312fec1d48c090bc3a4f13c6a01cb94bd5432 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:35 +0300 Subject: [PATCH 32/38] memory: tegra20-emc: Remove IRQ number from error message Remove IRQ number from error message since it doesn't add any useful information, especially because this number is virtual. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-6-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra20-emc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index d01b556a6d06..df758cebbd9d 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -1042,7 +1042,7 @@ static int tegra_emc_probe(struct platform_device *pdev) err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, dev_name(&pdev->dev), emc); if (err) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); + dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); return err; } From dedf62d6f17fc9cf0389602b6d3d7533cc218679 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:34 +0300 Subject: [PATCH 33/38] memory: tegra20-emc: Add devfreq support Add devfreq support to the Tegra20 EMC driver. Memory utilization statistics will be periodically polled from the memory controller and appropriate minimum clock rate will be selected by the devfreq governor. Signed-off-by: Dmitry Osipenko Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20201111011456.7875-5-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 3 +- drivers/memory/tegra/tegra20-emc.c | 90 ++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index ac3dfe155505..8cc1ec5be443 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -12,7 +12,8 @@ config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_2x_SOC - select PM_OPP + select DEVFREQ_GOV_SIMPLE_ONDEMAND + select PM_DEVFREQ help This driver is for the External Memory Controller (EMC) found on Tegra20 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index df758cebbd9d..0320d9df4a20 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -102,6 +103,10 @@ #define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4) +#define EMC_PWR_GATHER_CLEAR (1 << 8) +#define EMC_PWR_GATHER_DISABLE (2 << 8) +#define EMC_PWR_GATHER_ENABLE (3 << 8) + static const u16 emc_timing_registers[] = { EMC_RC, EMC_RFC, @@ -157,6 +162,7 @@ struct emc_timing { }; enum emc_rate_request_type { + EMC_RATE_DEVFREQ, EMC_RATE_DEBUG, EMC_RATE_ICC, EMC_RATE_TYPE_MAX, @@ -193,6 +199,8 @@ struct tegra_emc { /* protect shared rate-change code path */ struct mutex rate_lock; + + struct devfreq_simple_ondemand_data ondemand_data; }; static irqreturn_t tegra_emc_isr(int irq, void *data) @@ -1003,6 +1011,87 @@ static int tegra_emc_init_clk(struct tegra_emc *emc) return 0; } +static int tegra_emc_devfreq_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct tegra_emc *emc = dev_get_drvdata(dev); + struct dev_pm_opp *opp; + unsigned long rate; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (IS_ERR(opp)) { + dev_err(dev, "failed to find opp for %lu Hz\n", *freq); + return PTR_ERR(opp); + } + + rate = dev_pm_opp_get_freq(opp); + dev_pm_opp_put(opp); + + return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ); +} + +static int tegra_emc_devfreq_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct tegra_emc *emc = dev_get_drvdata(dev); + + /* freeze counters */ + writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL); + + /* + * busy_time: number of clocks EMC request was accepted + * total_time: number of clocks PWR_GATHER control was set to ENABLE + */ + stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT); + stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS); + stat->current_frequency = clk_get_rate(emc->clk); + + /* clear counters and restart */ + writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL); + writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL); + + return 0; +} + +static struct devfreq_dev_profile tegra_emc_devfreq_profile = { + .polling_ms = 30, + .target = tegra_emc_devfreq_target, + .get_dev_status = tegra_emc_devfreq_get_dev_status, +}; + +static int tegra_emc_devfreq_init(struct tegra_emc *emc) +{ + struct devfreq *devfreq; + + /* + * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold + * should be less than 50. Secondly, multiple active memory clients + * may cause over 20% of lost clock cycles due to stalls caused by + * competing memory accesses. This means that threshold should be + * set to a less than 30 in order to have a properly working governor. + */ + emc->ondemand_data.upthreshold = 20; + + /* + * Reset statistic gathers state, select global bandwidth for the + * statistics collection mode and set clocks counter saturation + * limit to maximum. + */ + writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL); + writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL); + writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT); + + devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile, + DEVFREQ_GOV_SIMPLE_ONDEMAND, + &emc->ondemand_data); + if (IS_ERR(devfreq)) { + dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq); + return PTR_ERR(devfreq); + } + + return 0; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -1058,6 +1147,7 @@ static int tegra_emc_probe(struct platform_device *pdev) tegra_emc_rate_requests_init(emc); tegra_emc_debugfs_init(emc); tegra_emc_interconnect_init(emc); + tegra_emc_devfreq_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some From 1d1564aabc697d53f19ef40b06d68dc8bde36ad4 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:36 +0300 Subject: [PATCH 34/38] memory: tegra30: Add FIFO sizes to memory clients The latency allowness is calculated based on buffering capabilities of memory clients. Add FIFO sizes to the Tegra30 memory clients. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-7-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra30.c | 66 ++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index b1990b4133d8..d0314f29608d 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -42,6 +42,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0, }, + .fifo_size = 16 * 2, }, { .id = 0x01, .name = "display0a", @@ -56,6 +57,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x02, .name = "display0ab", @@ -70,6 +72,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x03, .name = "display0b", @@ -84,6 +87,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x04, .name = "display0bb", @@ -98,6 +102,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x05, .name = "display0c", @@ -112,6 +117,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x06, .name = "display0cb", @@ -126,6 +132,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x07, .name = "display1b", @@ -140,6 +147,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x08, .name = "display1bb", @@ -154,6 +162,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x09, .name = "eppup", @@ -168,6 +177,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x17, }, + .fifo_size = 16 * 8, }, { .id = 0x0a, .name = "g2pr", @@ -182,6 +192,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x09, }, + .fifo_size = 16 * 64, }, { .id = 0x0b, .name = "g2sr", @@ -196,6 +207,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x09, }, + .fifo_size = 16 * 64, }, { .id = 0x0c, .name = "mpeunifbr", @@ -210,6 +222,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x50, }, + .fifo_size = 16 * 8, }, { .id = 0x0d, .name = "viruv", @@ -224,6 +237,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x2c, }, + .fifo_size = 16 * 8, }, { .id = 0x0e, .name = "afir", @@ -238,6 +252,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 32, }, { .id = 0x0f, .name = "avpcarm7r", @@ -252,6 +267,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x04, }, + .fifo_size = 16 * 2, }, { .id = 0x10, .name = "displayhc", @@ -266,6 +282,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 2, }, { .id = 0x11, .name = "displayhcb", @@ -280,6 +297,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 2, }, { .id = 0x12, .name = "fdcdrd", @@ -294,6 +312,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x13, .name = "fdcdrd2", @@ -308,6 +327,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x14, .name = "g2dr", @@ -322,6 +342,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x15, .name = "hdar", @@ -336,6 +357,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 16, }, { .id = 0x16, .name = "host1xdmar", @@ -350,6 +372,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x05, }, + .fifo_size = 16 * 16, }, { .id = 0x17, .name = "host1xr", @@ -364,6 +387,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x50, }, + .fifo_size = 16 * 8, }, { .id = 0x18, .name = "idxsrd", @@ -378,6 +402,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x19, .name = "idxsrd2", @@ -392,6 +417,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x1a, .name = "mpe_ipred", @@ -406,6 +432,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x80, }, + .fifo_size = 16 * 2, }, { .id = 0x1b, .name = "mpeamemrd", @@ -420,6 +447,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x42, }, + .fifo_size = 16 * 64, }, { .id = 0x1c, .name = "mpecsrd", @@ -434,6 +462,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 8, }, { .id = 0x1d, .name = "ppcsahbdmar", @@ -448,6 +477,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 2, }, { .id = 0x1e, .name = "ppcsahbslvr", @@ -462,6 +492,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x12, }, + .fifo_size = 16 * 8, }, { .id = 0x1f, .name = "satar", @@ -476,6 +507,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x33, }, + .fifo_size = 16 * 32, }, { .id = 0x20, .name = "texsrd", @@ -490,6 +522,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x21, .name = "texsrd2", @@ -504,6 +537,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x22, .name = "vdebsevr", @@ -518,6 +552,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 8, }, { .id = 0x23, .name = "vdember", @@ -532,6 +567,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xd0, }, + .fifo_size = 16 * 4, }, { .id = 0x24, .name = "vdemcer", @@ -546,6 +582,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x2a, }, + .fifo_size = 16 * 16, }, { .id = 0x25, .name = "vdetper", @@ -560,6 +597,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x74, }, + .fifo_size = 16 * 16, }, { .id = 0x26, .name = "mpcorelpr", @@ -570,6 +608,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x04, }, + .fifo_size = 16 * 14, }, { .id = 0x27, .name = "mpcorer", @@ -580,6 +619,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x04, }, + .fifo_size = 16 * 14, }, { .id = 0x28, .name = "eppu", @@ -594,6 +634,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x6c, }, + .fifo_size = 16 * 64, }, { .id = 0x29, .name = "eppv", @@ -608,6 +649,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x6c, }, + .fifo_size = 16 * 64, }, { .id = 0x2a, .name = "eppy", @@ -622,6 +664,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x6c, }, + .fifo_size = 16 * 64, }, { .id = 0x2b, .name = "mpeunifbw", @@ -636,6 +679,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 8, }, { .id = 0x2c, .name = "viwsb", @@ -650,6 +694,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x12, }, + .fifo_size = 16 * 64, }, { .id = 0x2d, .name = "viwu", @@ -664,6 +709,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xb2, }, + .fifo_size = 16 * 64, }, { .id = 0x2e, .name = "viwv", @@ -678,6 +724,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xb2, }, + .fifo_size = 16 * 64, }, { .id = 0x2f, .name = "viwy", @@ -692,6 +739,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x12, }, + .fifo_size = 16 * 64, }, { .id = 0x30, .name = "g2dw", @@ -706,6 +754,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x9, }, + .fifo_size = 16 * 128, }, { .id = 0x31, .name = "afiw", @@ -720,6 +769,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0c, }, + .fifo_size = 16 * 32, }, { .id = 0x32, .name = "avpcarm7w", @@ -734,6 +784,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0e, }, + .fifo_size = 16 * 2, }, { .id = 0x33, .name = "fdcdwr", @@ -748,6 +799,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x34, .name = "fdcdwr2", @@ -762,6 +814,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x35, .name = "hdaw", @@ -776,6 +829,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 16, }, { .id = 0x36, .name = "host1xw", @@ -790,6 +844,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 32, }, { .id = 0x37, .name = "ispw", @@ -804,6 +859,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 64, }, { .id = 0x38, .name = "mpcorelpw", @@ -814,6 +870,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0e, }, + .fifo_size = 16 * 24, }, { .id = 0x39, .name = "mpcorew", @@ -824,6 +881,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0e, }, + .fifo_size = 16 * 24, }, { .id = 0x3a, .name = "mpecswr", @@ -838,6 +896,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 8, }, { .id = 0x3b, .name = "ppcsahbdmaw", @@ -852,6 +911,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 2, }, { .id = 0x3c, .name = "ppcsahbslvw", @@ -866,6 +926,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x06, }, + .fifo_size = 16 * 4, }, { .id = 0x3d, .name = "sataw", @@ -880,6 +941,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x33, }, + .fifo_size = 16 * 32, }, { .id = 0x3e, .name = "vdebsevw", @@ -894,6 +956,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 4, }, { .id = 0x3f, .name = "vdedbgw", @@ -908,6 +971,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 16, }, { .id = 0x40, .name = "vdembew", @@ -922,6 +986,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x42, }, + .fifo_size = 16 * 2, }, { .id = 0x41, .name = "vdetpmw", @@ -936,6 +1001,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x2a, }, + .fifo_size = 16 * 16, }, }; From 0c56eda86f8cad705d7d14e81e0e4efaeeaf4613 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:37 +0300 Subject: [PATCH 35/38] memory: tegra30-emc: Make driver modular Add modularization support to the Tegra30 EMC driver, which now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-8-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/mc.c | 3 +++ drivers/memory/tegra/tegra30-emc.c | 17 ++++++++++++----- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 8cc1ec5be443..2a4a16bcf91c 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -21,7 +21,7 @@ config TEGRA20_EMC external memory. config TEGRA30_EMC - bool "NVIDIA Tegra30 External Memory Controller driver" + tristate "NVIDIA Tegra30 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_3x_SOC help diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index a7e6a8e4c95a..44064de962c2 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -346,6 +347,7 @@ int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) return 0; } +EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration); unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) { @@ -357,6 +359,7 @@ unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) return dram_count; } +EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); static int load_one_timing(struct tegra_mc *mc, struct tegra_mc_timing *timing, diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 1be28e28ec34..d0926088360a 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1330,6 +1330,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; unset_cb: @@ -1380,6 +1387,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra30-emc", }, {}, }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct platform_driver tegra_emc_driver = { .probe = tegra_emc_probe, @@ -1390,9 +1398,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int __init tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Dmitry Osipenko "); +MODULE_DESCRIPTION("NVIDIA Tegra30 EMC driver"); +MODULE_LICENSE("GPL v2"); From bf25f3fceffa9e4e5b5a59ed51511ec5ba6a6036 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:38 +0300 Subject: [PATCH 36/38] memory: tegra30-emc: Continue probing if timings are missing in device-tree EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-9-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra30-emc.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index d0926088360a..3488786da03b 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -988,6 +988,11 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev) u32 value, ram_code; int err; + if (of_get_child_count(dev->of_node) == 0) { + dev_info(dev, "device-tree doesn't have memory timings\n"); + return NULL; + } + ram_code = tegra_read_ram_code(); for_each_child_of_node(dev->of_node, np) { @@ -1057,6 +1062,9 @@ static long emc_round_rate(unsigned long rate, struct tegra_emc *emc = arg; unsigned int i; + if (!emc->num_timings) + return clk_get_rate(emc->clk); + min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); for (i = 0; i < emc->num_timings; i++) { @@ -1262,16 +1270,6 @@ static int tegra_emc_probe(struct platform_device *pdev) struct tegra_emc *emc; int err; - if (of_get_child_count(pdev->dev.of_node) == 0) { - dev_info(&pdev->dev, - "device-tree node doesn't have memory timings\n"); - return -ENODEV; - } - - np = emc_find_node_by_ram_code(&pdev->dev); - if (!np) - return -EINVAL; - emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); if (!emc) { of_node_put(np); @@ -1285,10 +1283,13 @@ static int tegra_emc_probe(struct platform_device *pdev) emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; - err = emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) - return err; + np = emc_find_node_by_ram_code(&pdev->dev); + if (np) { + err = emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + } emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) From 4a91b11c0a100532c466e07a1372d134ab0e753d Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 7 Oct 2020 17:37:46 -0700 Subject: [PATCH 37/38] memory: tegra: Complete tegra210_swgroups According to Tegra X1 TRM, there are missing swgroups in the tegra210_swgroups list. So this patch adds them to the list. Note that the TEGRA_SWGROUP_GPU (in list) should be actually TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps TEGRA_SWGROUP_GPU (in list) as it is. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-6-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra210.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index b400802c9f14..b3bbc5a05ba1 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1028,6 +1028,8 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = { { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 }, + { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 }, + { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c }, { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 }, { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 }, { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, @@ -1036,19 +1038,27 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = { { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c }, { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 }, { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, + { .name = "ppcs1", .swgroup = TEGRA_SWGROUP_PPCS1, .reg = 0x298 }, + { .name = "dc1", .swgroup = TEGRA_SWGROUP_DC1, .reg = 0xa88 }, { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 }, { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 }, { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c }, { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 }, { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac }, + { .name = "ppcs2", .swgroup = TEGRA_SWGROUP_PPCS2, .reg = 0xab0 }, { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 }, { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 }, { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc }, { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 }, + { .name = "hc1", .swgroup = TEGRA_SWGROUP_HC1, .reg = 0xac4 }, + { .name = "se1", .swgroup = TEGRA_SWGROUP_SE1, .reg = 0xac8 }, { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc }, { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 }, { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 }, + { .name = "tsec1", .swgroup = TEGRA_SWGROUP_TSEC1, .reg = 0xad8 }, + { .name = "tsecb1", .swgroup = TEGRA_SWGROUP_TSECB1, .reg = 0xadc }, + { .name = "nvdec1", .swgroup = TEGRA_SWGROUP_NVDEC1, .reg = 0xae0 }, }; static const unsigned int tegra210_group_display[] = { From 0e1bcf2c05d0a681c04351fbd60812aea99354b6 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Thu, 19 Nov 2020 12:52:44 -0700 Subject: [PATCH 38/38] memory: tegra30-emc: Remove unnecessary of_node_put in tegra_emc_probe Clang warns: drivers/memory/tegra/tegra30-emc.c:1275:15: warning: variable 'np' is uninitialized when used here [-Wuninitialized] of_node_put(np); ^~ drivers/memory/tegra/tegra30-emc.c:1269:24: note: initialize the variable 'np' to silence this warning There does not need to be an of_node_put call in this error handling block after the shuffling of the np assignment. Remove it so there is no use of uninitialized memory. Fixes: 5e00fd90183a ("memory: tegra30-emc: Continue probing if timings are missing in device-tree") Signed-off-by: Nathan Chancellor Reviewed-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201119195244.1517236-1-natechancellor@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra30-emc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 3488786da03b..93f9002d32ad 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1271,10 +1271,8 @@ static int tegra_emc_probe(struct platform_device *pdev) int err; emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); - if (!emc) { - of_node_put(np); + if (!emc) return -ENOMEM; - } emc->mc = devm_tegra_memory_controller_get(&pdev->dev); if (IS_ERR(emc->mc))