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x86/mm/pat: Emulate PAT when it is disabled
In the case when PAT is disabled on the command line with
"nopat" or when virtualization doesn't support PAT (correctly) -
see
9d34cfdf47 ("x86: Don't rely on VMWare emulating PAT MSR correctly").
we emulate it using the PWT and PCD cache attribute bits. Get
rid of boot_pat_state while at it.
Based on a conglomerate patch from Toshi Kani.
Signed-off-by: Borislav Petkov <[email protected]>
Reviewed-by: Toshi Kani <[email protected]>
Acked-by: Juergen Gross <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: [email protected]
Cc: H. Peter Anvin <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Luis R. Rodriguez <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: linux-mm <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
This commit is contained in:
Borislav Petkov authored and Ingo Molnar committed
1 parent
9dac629094
commit
9cd25aac1f
4 files changed
+60
-34
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@@ -6,7 +6,7 @@
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bool pat_enabled(void);
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extern void pat_init(void);
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void pat_init_cache_modes(void);
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void pat_init_cache_modes(u64);
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extern int reserve_memtype(u64 start, u64 end,
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enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm);
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+3
-3
@@ -40,7 +40,7 @@
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*/
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uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
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[_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
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[_PAGE_CACHE_MODE_WC ] = _PAGE_PWT | 0 ,
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[_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
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[_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
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[_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD,
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[_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
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@@ -50,11 +50,11 @@ EXPORT_SYMBOL(__cachemode2pte_tbl);
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uint8_t __pte2cachemode_tbl[8] = {
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[__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
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[__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_WC,
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[__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
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[__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
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[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC,
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[__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
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[__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WC,
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[__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
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[__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
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[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
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};
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+53
-28
@@ -68,8 +68,6 @@ static int __init pat_debug_setup(char *str)
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}
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__setup("debugpat", pat_debug_setup);
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static u64 __read_mostly boot_pat_state;
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#ifdef CONFIG_X86_PAT
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/*
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* X86 PAT uses page flags WC and Uncached together to keep track of
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@@ -177,14 +175,12 @@ static enum page_cache_mode pat_get_cache_mode(unsigned pat_val, char *msg)
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* configuration.
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* Using lower indices is preferred, so we start with highest index.
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*/
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void pat_init_cache_modes(void)
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void pat_init_cache_modes(u64 pat)
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{
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int i;
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enum page_cache_mode cache;
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char pat_msg[33];
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u64 pat;
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int i;
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rdmsrl(MSR_IA32_CR_PAT, pat);
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pat_msg[32] = 0;
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for (i = 7; i >= 0; i--) {
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cache = pat_get_cache_mode((pat >> (i * 8)) & 7,
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@@ -198,24 +194,33 @@ void pat_init_cache_modes(void)
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static void pat_bsp_init(u64 pat)
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{
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u64 tmp_pat;
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if (!cpu_has_pat) {
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pat_disable("PAT not supported by CPU.");
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return;
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}
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rdmsrl(MSR_IA32_CR_PAT, boot_pat_state);
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if (!boot_pat_state) {
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if (!pat_enabled())
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goto done;
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rdmsrl(MSR_IA32_CR_PAT, tmp_pat);
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if (!tmp_pat) {
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pat_disable("PAT MSR is 0, disabled.");
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return;
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}
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wrmsrl(MSR_IA32_CR_PAT, pat);
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pat_init_cache_modes();
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done:
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pat_init_cache_modes(pat);
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}
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static void pat_ap_init(u64 pat)
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{
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if (!pat_enabled())
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return;
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if (!cpu_has_pat) {
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/*
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* If this happens we are on a secondary CPU, but switched to
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@@ -231,25 +236,45 @@ void pat_init(void)
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{
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u64 pat;
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if (!pat_enabled())
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return;
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/*
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* Set PWT to Write-Combining. All other bits stay the same:
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*
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* PTE encoding used in Linux:
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* PAT
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* |PCD
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* ||PWT
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* |||
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* 000 WB _PAGE_CACHE_WB
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* 001 WC _PAGE_CACHE_WC
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* 010 UC- _PAGE_CACHE_UC_MINUS
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* 011 UC _PAGE_CACHE_UC
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* PAT bit unused
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*/
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pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
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PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
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if (!pat_enabled()) {
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/*
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* No PAT. Emulate the PAT table that corresponds to the two
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* cache bits, PWT (Write Through) and PCD (Cache Disable). This
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* setup is the same as the BIOS default setup when the system
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* has PAT but the "nopat" boot option has been specified. This
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* emulated PAT table is used when MSR_IA32_CR_PAT returns 0.
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*
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* PTE encoding used:
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*
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* PCD
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* |PWT PAT
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* || slot
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* 00 0 WB : _PAGE_CACHE_MODE_WB
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* 01 1 WT : _PAGE_CACHE_MODE_WT
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* 10 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
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* 11 3 UC : _PAGE_CACHE_MODE_UC
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*
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* NOTE: When WC or WP is used, it is redirected to UC- per
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* the default setup in __cachemode2pte_tbl[].
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*/
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pat = PAT(0, WB) | PAT(1, WT) | PAT(2, UC_MINUS) | PAT(3, UC) |
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PAT(4, WB) | PAT(5, WT) | PAT(6, UC_MINUS) | PAT(7, UC);
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} else {
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/*
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* PTE encoding used in Linux:
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* PAT
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* |PCD
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* ||PWT
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* |||
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* 000 WB _PAGE_CACHE_WB
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* 001 WC _PAGE_CACHE_WC
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* 010 UC- _PAGE_CACHE_UC_MINUS
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* 011 UC _PAGE_CACHE_UC
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* PAT bit unused
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*/
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pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
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PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
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}
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if (!boot_cpu_done) {
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pat_bsp_init(pat);
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@@ -1467,6 +1467,7 @@ asmlinkage __visible void __init xen_start_kernel(void)
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{
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struct physdev_set_iopl set_iopl;
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unsigned long initrd_start = 0;
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u64 pat;
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int rc;
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if (!xen_start_info)
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@@ -1574,8 +1575,8 @@ asmlinkage __visible void __init xen_start_kernel(void)
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* Modify the cache mode translation tables to match Xen's PAT
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* configuration.
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*/
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pat_init_cache_modes();
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rdmsrl(MSR_IA32_CR_PAT, pat);
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pat_init_cache_modes(pat);
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/* keep using Xen gdt for now; no urgent need to change it */
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