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[S390] __div64_32 for 31 bit.

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The clocksource infrastructure introduced with commit
ad596171ed broke 31 bit s390.
The reason is that the do_div() primitive for 31 bit always
had a restriction: it could only divide an unsigned 64 bit
integer by an unsigned 31 bit integer. The clocksource code
now uses do_div() with a base value that has the most
significant bit set. The result is that clock->cycle_interval
has a funny value which causes the linux time to jump around
like mad.
The solution is "obvious": implement a proper __div64_32
function for 31 bit s390.

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Martin Schwidefsky
2006-09-28 16:55:39 +02:00
parent 1fce518e8e
commit d9f7a745d5
4 changed files with 156 additions and 48 deletions
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48
include/asm-s390/div64.h
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@@ -1,49 +1 @@
#ifndef __S390_DIV64
#define __S390_DIV64
#ifndef __s390x__
/* for do_div "base" needs to be smaller than 2^31-1 */
#define do_div(n, base) ({ \
unsigned long long __n = (n); \
unsigned long __r; \
\
asm (" slr 0,0\n" \
" l 1,%1\n" \
" srdl 0,1\n" \
" dr 0,%2\n" \
" alr 1,1\n" \
" alr 0,0\n" \
" lhi 2,1\n" \
" n 2,%1\n" \
" alr 0,2\n" \
" clr 0,%2\n" \
" jl 0f\n" \
" slr 0,%2\n" \
" ahi 1,1\n" \
"0: st 1,%1\n" \
" l 1,4+%1\n" \
" srdl 0,1\n" \
" dr 0,%2\n" \
" alr 1,1\n" \
" alr 0,0\n" \
" lhi 2,1\n" \
" n 2,4+%1\n" \
" alr 0,2\n" \
" clr 0,%2\n" \
" jl 1f\n" \
" slr 0,%2\n" \
" ahi 1,1\n" \
"1: st 1,4+%1\n" \
" lr %0,0" \
: "=d" (__r), "=m" (__n) \
: "d" (base), "m" (__n) : "0", "1", "2", "cc" ); \
(n) = (__n); \
__r; \
})
#else /* __s390x__ */
#include <asm-generic/div64.h>
#endif /* __s390x__ */
#endif