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drm/i915: add more Haswell PCI IDs
Also properly indent the HB IDs. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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committed by
Daniel Vetter
parent
5ab3633d69
commit
da612d880f
@@ -239,16 +239,45 @@
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A
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#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */
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#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30
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#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */
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#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */
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#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402
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#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412
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#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */
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#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG 0x0422
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#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */
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#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406
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#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416
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#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */
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#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG 0x0426
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#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */
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#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a
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#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG 0x041a
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV 0x0c16 /* SDV */
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#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04
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#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG 0x042a
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#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG 0x0C02
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG 0x0C12
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG 0x0C22
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG 0x0C06
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG 0x0C16
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG 0x0C26
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG 0x0C0A
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG 0x0C1A
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG 0x0C2A
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#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG 0x0A02
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#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG 0x0A12
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#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG 0x0A22
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#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG 0x0A06
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#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG 0x0A16
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#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG 0x0A26
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#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG 0x0A0A
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#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG 0x0A1A
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#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG 0x0A2A
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#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG 0x0D12
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#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG 0x0D22
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#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG 0x0D32
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#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG 0x0D16
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#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG 0x0D26
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#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG 0x0D36
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#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG 0x0D1A
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#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG 0x0D2A
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#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG 0x0D3A
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#endif
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@@ -1502,15 +1502,73 @@ static const struct intel_gtt_driver_description {
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV,
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{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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{ 0, NULL, NULL }
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};
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