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[POWERPC] Separate IRQ config / register set from main header

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There is no need to expose these settings outside the scope
of the interrupt controller code itself.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Sylvain Munaut
2006-11-27 14:16:26 -07:00
committed by Paul Mackerras
parent b9cf5d8e2e
commit e65fdfd6ca
3 changed files with 54 additions and 37 deletions
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37
include/asm-powerpc/mpc52xx.h
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@@ -19,49 +19,12 @@
#endif /* __ASSEMBLY__ */
/* ======================================================================== */
/* HW IRQ mapping */
/* ======================================================================== */
#define MPC52xx_IRQ_L1_CRIT (0)
#define MPC52xx_IRQ_L1_MAIN (1)
#define MPC52xx_IRQ_L1_PERP (2)
#define MPC52xx_IRQ_L1_SDMA (3)
#define MPC52xx_IRQ_L1_OFFSET (6)
#define MPC52xx_IRQ_L1_MASK (0xc0)
#define MPC52xx_IRQ_L2_OFFSET (0)
#define MPC52xx_IRQ_L2_MASK (0x3f)
#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
/* ======================================================================== */
/* Structures mapping of some unit register set */
/* ======================================================================== */
#ifndef __ASSEMBLY__
/* Interrupt controller Register set */
struct mpc52xx_intr {
u32 per_mask; /* INTR + 0x00 */
u32 per_pri1; /* INTR + 0x04 */
u32 per_pri2; /* INTR + 0x08 */
u32 per_pri3; /* INTR + 0x0c */
u32 ctrl; /* INTR + 0x10 */
u32 main_mask; /* INTR + 0x14 */
u32 main_pri1; /* INTR + 0x18 */
u32 main_pri2; /* INTR + 0x1c */
u32 reserved1; /* INTR + 0x20 */
u32 enc_status; /* INTR + 0x24 */
u32 crit_status; /* INTR + 0x28 */
u32 main_status; /* INTR + 0x2c */
u32 per_status; /* INTR + 0x30 */
u32 reserved2; /* INTR + 0x34 */
u32 per_error; /* INTR + 0x38 */
};
/* Memory Mapping Control */
struct mpc52xx_mmap_ctl {
u32 mbar; /* MMAP_CTRL + 0x00 */