mirror of
https://github.com/torvalds/linux.git
synced 2026-09-21 20:17:00 -04:00
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Fix wreckage after removal of tickadj; convert to GENERIC_TIME. [MIPS] DECstation defconfig update [MIPS] Fix size of zones_size and zholes_size array [MIPS] BCM1480: Mask pending interrupts against c0_status.im. [MIPS] SB1250: Interrupt handler fixes [MIPS] Remove IT8172-based platforms, ITE 8172G and Globespan IVR support. [MIPS] Remove Atlas and SEAD from feature-removal-schedule. [MIPS] Remove Jaguar and Ocelot family from feature list. [MIPS] BCM1250: TRDY timeout tweaks for Broadcom SiByte systems [MIPS] Remove dead DECstation boot code [MIPS] Let gcc align 'struct pt_regs' on 8 bytes boundary
This commit is contained in:
Linus Torvalds
@@ -124,12 +124,6 @@
|
||||
#define MACH_MOMENCO_JAGUAR_ATX 3
|
||||
#define MACH_MOMENCO_OCELOT_3 4
|
||||
|
||||
/*
|
||||
* Valid machtype for group ITE
|
||||
*/
|
||||
#define MACH_GROUP_ITE 13 /* ITE Semi Eval Boards */
|
||||
#define MACH_QED_4N_S01B 0 /* ITE8172 based eval board */
|
||||
|
||||
/*
|
||||
* Valid machtype for group PHILIPS
|
||||
*/
|
||||
@@ -138,12 +132,6 @@
|
||||
#define MACH_PHILIPS_VELO 1 /* Velo */
|
||||
#define MACH_PHILIPS_JBS 2 /* JBS */
|
||||
|
||||
/*
|
||||
* Valid machtype for group Globespan
|
||||
*/
|
||||
#define MACH_GROUP_GLOBESPAN 15 /* Globespan */
|
||||
#define MACH_IVR 0 /* IVR eval board */
|
||||
|
||||
/*
|
||||
* Valid machtype for group SIBYTE
|
||||
*/
|
||||
|
||||
@@ -1,348 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* IT8172 system controller defines.
|
||||
*
|
||||
* Copyright 2000 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __IT8172__H__
|
||||
#define __IT8172__H__
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
#define IT8172_BASE 0x18000000
|
||||
#define IT8172_PCI_IO_BASE 0x14000000
|
||||
#define IT8172_PCI_MEM_BASE 0x10000000
|
||||
|
||||
// System registers offsets from IT8172_BASE
|
||||
#define IT_CMFPCR 0x0
|
||||
#define IT_DSRR 0x2
|
||||
#define IT_PCDCR 0x4
|
||||
#define IT_SPLLCR 0x6
|
||||
#define IT_CIDR 0x10
|
||||
#define IT_CRNR 0x12
|
||||
#define IT_CPUTR 0x14
|
||||
#define IT_CTCR 0x16
|
||||
#define IT_SDPR 0xF0
|
||||
|
||||
// Power management register offset from IT8172_PCI_IO_BASE
|
||||
// Power Management Device Standby Register
|
||||
#define IT_PM_DSR 0x15800
|
||||
|
||||
#define IT_PM_DSR_TMR0SB 0x0001
|
||||
#define IT_PM_DSR_TMR1SB 0x0002
|
||||
#define IT_PM_DSR_CIR0SB 0x0004
|
||||
#define IT_PM_DSR_CIR1SB 0x0008
|
||||
#define IT_PM_DSR_SCR0SB 0x0010
|
||||
#define IT_PM_DSR_SCR1SB 0x0020
|
||||
#define IT_PM_DSR_PPSB 0x0040
|
||||
#define IT_PM_DSR_I2CSB 0x0080
|
||||
#define IT_PM_DSR_UARTSB 0x0100
|
||||
#define IT_PM_DSR_IDESB 0x0200
|
||||
#define IT_PM_DSR_ACSB 0x0400
|
||||
#define IT_PM_DSR_M68KSB 0x0800
|
||||
|
||||
// Power Management PCI Device Software Reset Register
|
||||
#define IT_PM_PCISR 0x15802
|
||||
|
||||
#define IT_PM_PCISR_IDESR 0x0001
|
||||
#define IT_PM_PCISR_CDMASR 0x0002
|
||||
#define IT_PM_PCISR_USBSR 0x0004
|
||||
#define IT_PM_PCISR_DMASR 0x0008
|
||||
#define IT_PM_PCISR_ACSR 0x0010
|
||||
#define IT_PM_PCISR_MEMSR 0x0020
|
||||
#define IT_PM_PCISR_68KSR 0x0040
|
||||
|
||||
|
||||
// PCI Configuration address and data register offsets
|
||||
// from IT8172_BASE
|
||||
#define IT_CONFADDR 0x4000
|
||||
#define IT_BUSNUM_SHF 16
|
||||
#define IT_DEVNUM_SHF 11
|
||||
#define IT_FUNCNUM_SHF 8
|
||||
#define IT_REGNUM_SHF 2
|
||||
|
||||
#define IT_CONFDATA 0x4004
|
||||
|
||||
// PCI configuration header common register offsets
|
||||
#define IT_VID 0x00
|
||||
#define IT_DID 0x02
|
||||
#define IT_PCICMD 0x04
|
||||
#define IT_PCISTS 0x06
|
||||
#define IT_RID 0x08
|
||||
#define IT_CLASSC 0x09
|
||||
#define IT_HEADT 0x0E
|
||||
#define IT_SERIRQC 0x49
|
||||
|
||||
// PCI to Internal/LPC Bus Bridge configuration header register offset
|
||||
#define IT_P2I_BCR 0x4C
|
||||
#define IT_P2I_D0IOSC 0x50
|
||||
#define IT_P2I_D1IOSC 0x54
|
||||
#define IT_P2I_D2IOSC 0x58
|
||||
#define IT_P2I_D3IOSC 0x5C
|
||||
#define IT_P2I_D4IOSC 0x60
|
||||
#define IT_P2I_D5IOSC 0x64
|
||||
#define IT_P2I_D6IOSC 0x68
|
||||
#define IT_P2I_D7IOSC 0x6C
|
||||
#define IT_P2I_D8IOSC 0x70
|
||||
#define IT_P2I_D9IOSC 0x74
|
||||
#define IT_P2I_D10IOSC 0x78
|
||||
#define IT_P2I_D11IOSC 0x7C
|
||||
|
||||
// Memory controller register offsets from IT8172_BASE
|
||||
#define IT_MC_SDRMR 0x1000
|
||||
#define IT_MC_SDRTR 0x1004
|
||||
#define IT_MC_MCR 0x1008
|
||||
#define IT_MC_SDTYPE 0x100C
|
||||
#define IT_MC_WPBA 0x1010
|
||||
#define IT_MC_WPTA 0x1014
|
||||
#define IT_MC_HATR 0x1018
|
||||
#define IT_MC_PCICR 0x101C
|
||||
|
||||
// Flash/ROM control register offsets from IT8172_BASE
|
||||
#define IT_FC_BRCR 0x2000
|
||||
#define IT_FC_FCR 0x2004
|
||||
#define IT_FC_DCR 0x2008
|
||||
|
||||
// M68K interface bridge configuration header register offset
|
||||
#define IT_M68K_MBCSR 0x54
|
||||
#define IT_M68K_TMR 0x58
|
||||
#define IT_M68K_BCR 0x5C
|
||||
#define IT_M68K_BSR 0x5D
|
||||
#define IT_M68K_DTR 0x5F
|
||||
|
||||
// Register offset from IT8172_PCI_IO_BASE
|
||||
// These registers are accessible through 8172 PCI IO window.
|
||||
|
||||
// INTC
|
||||
#define IT_INTC_BASE 0x10000
|
||||
#define IT_INTC_LBDNIRR 0x10000
|
||||
#define IT_INTC_LBDNIMR 0x10002
|
||||
#define IT_INTC_LBDNITR 0x10004
|
||||
#define IT_INTC_LBDNIAR 0x10006
|
||||
#define IT_INTC_LPCNIRR 0x10010
|
||||
#define IT_INTC_LPCNIMR 0x10012
|
||||
#define IT_INTC_LPCNITR 0x10014
|
||||
#define IT_INTC_LPCNIAR 0x10016
|
||||
#define IT_INTC_PDNIRR 0x10020
|
||||
#define IT_INTC_PDNIMR 0x10022
|
||||
#define IT_INTC_PDNITR 0x10024
|
||||
#define IT_INTC_PDNIAR 0x10026
|
||||
#define IT_INTC_UMNIRR 0x10030
|
||||
#define IT_INTC_UMNITR 0x10034
|
||||
#define IT_INTC_UMNIAR 0x10036
|
||||
#define IT_INTC_TYPER 0x107FE
|
||||
|
||||
// IT8172 PCI device number
|
||||
#define IT_C2P_DEVICE 0
|
||||
#define IT_AUDIO_DEVICE 1
|
||||
#define IT_DMAC_DEVICE 1
|
||||
#define IT_CDMAC_DEVICE 1
|
||||
#define IT_USB_DEVICE 1
|
||||
#define IT_P2I_DEVICE 1
|
||||
#define IT_IDE_DEVICE 1
|
||||
#define IT_M68K_DEVICE 1
|
||||
|
||||
// IT8172 PCI function number
|
||||
#define IT_C2P_FUNCION 0
|
||||
#define IT_AUDIO_FUNCTION 0
|
||||
#define IT_DMAC_FUNCTION 1
|
||||
#define IT_CDMAC_FUNCTION 2
|
||||
#define IT_USB_FUNCTION 3
|
||||
#define IT_P2I_FUNCTION 4
|
||||
#define IT_IDE_FUNCTION 5
|
||||
#define IT_M68K_FUNCTION 6
|
||||
|
||||
// IT8172 GPIO
|
||||
#define IT_GPADR 0x13800
|
||||
#define IT_GPBDR 0x13808
|
||||
#define IT_GPCDR 0x13810
|
||||
#define IT_GPACR 0x13802
|
||||
#define IT_GPBCR 0x1380A
|
||||
#define IT_GPCCR 0x13812
|
||||
#define IT_GPAICR 0x13804
|
||||
#define IT_GPBICR 0x1380C
|
||||
#define IT_GPCICR 0x13814
|
||||
#define IT_GPAISR 0x13806
|
||||
#define IT_GPBISR 0x1380E
|
||||
#define IT_GPCISR 0x13816
|
||||
#define IT_GCR 0x13818
|
||||
|
||||
// IT8172 RTC
|
||||
#define IT_RTC_BASE 0x14800
|
||||
#define IT_RTC_CENTURY 0x14808
|
||||
|
||||
#define IT_RTC_RIR0 0x00
|
||||
#define IT_RTC_RTR0 0x01
|
||||
#define IT_RTC_RIR1 0x02
|
||||
#define IT_RTC_RTR1 0x03
|
||||
#define IT_RTC_RIR2 0x04
|
||||
#define IT_RTC_RTR2 0x05
|
||||
#define IT_RTC_RCTR 0x08
|
||||
#define IT_RTC_RA 0x0A
|
||||
#define IT_RTC_RB 0x0B
|
||||
#define IT_RTC_RC 0x0C
|
||||
#define IT_RTC_RD 0x0D
|
||||
|
||||
#define RTC_SEC_INDEX 0x00
|
||||
#define RTC_MIN_INDEX 0x02
|
||||
#define RTC_HOUR_INDEX 0x04
|
||||
#define RTC_DAY_INDEX 0x06
|
||||
#define RTC_DATE_INDEX 0x07
|
||||
#define RTC_MONTH_INDEX 0x08
|
||||
#define RTC_YEAR_INDEX 0x09
|
||||
|
||||
// IT8172 internal device registers
|
||||
#define IT_TIMER_BASE 0x10800
|
||||
#define IT_CIR0_BASE 0x11000
|
||||
#define IT_UART_BASE 0x11800
|
||||
#define IT_SCR0_BASE 0x12000
|
||||
#define IT_SCR1_BASE 0x12800
|
||||
#define IT_PP_BASE 0x13000
|
||||
#define IT_I2C_BASE 0x14000
|
||||
#define IT_CIR1_BASE 0x15000
|
||||
|
||||
// IT8172 Smart Card Reader offsets from IT_SCR*_BASE
|
||||
#define IT_SCR_SFR 0x08
|
||||
#define IT_SCR_SCDR 0x09
|
||||
|
||||
// IT8172 IT_SCR_SFR bit definition & mask
|
||||
#define IT_SCR_SFR_GATE_UART 0x40
|
||||
#define IT_SCR_SFR_GATE_UART_BIT 6
|
||||
#define IT_SCR_SFR_GATE_UART_OFF 0
|
||||
#define IT_SCR_SFR_GATE_UART_ON 1
|
||||
#define IT_SCR_SFR_FET_CHARGE 0x30
|
||||
#define IT_SCR_SFR_FET_CHARGE_BIT 4
|
||||
#define IT_SCR_SFR_FET_CHARGE_3_3_US 3
|
||||
#define IT_SCR_SFR_FET_CHARGE_13_US 2
|
||||
#define IT_SCR_SFR_FET_CHARGE_53_US 1
|
||||
#define IT_SCR_SFR_FET_CHARGE_213_US 0
|
||||
#define IT_SCR_SFR_CARD_FREQ 0x0C
|
||||
#define IT_SCR_SFR_CARD_FREQ_BIT 2
|
||||
#define IT_SCR_SFR_CARD_FREQ_STOP 3
|
||||
#define IT_SCR_SFR_CARD_FREQ_3_5_MHZ 0
|
||||
#define IT_SCR_SFR_CARD_FREQ_7_1_MHZ 2
|
||||
#define IT_SCR_SFR_CARD_FREQ_96_DIV_MHZ 1
|
||||
#define IT_SCR_SFR_FET_ACTIVE 0x02
|
||||
#define IT_SCR_SFR_FET_ACTIVE_BIT 1
|
||||
#define IT_SCR_SFR_FET_ACTIVE_INVERT 0
|
||||
#define IT_SCR_SFR_FET_ACTIVE_NONINVERT 1
|
||||
#define IT_SCR_SFR_ENABLE 0x01
|
||||
#define IT_SCR_SFR_ENABLE_BIT 0
|
||||
#define IT_SCR_SFR_ENABLE_OFF 0
|
||||
#define IT_SCR_SFR_ENABLE_ON 1
|
||||
|
||||
// IT8172 IT_SCR_SCDR bit definition & mask
|
||||
#define IT_SCR_SCDR_RESET_MODE 0x80
|
||||
#define IT_SCR_SCDR_RESET_MODE_BIT 7
|
||||
#define IT_SCR_SCDR_RESET_MODE_ASYNC 0
|
||||
#define IT_SCR_SCDR_RESET_MODE_SYNC 1
|
||||
#define IT_SCR_SCDR_DIVISOR 0x7F
|
||||
#define IT_SCR_SCDR_DIVISOR_BIT 0
|
||||
#define IT_SCR_SCDR_DIVISOR_STOP_VAL_1 0x00
|
||||
#define IT_SCR_SCDR_DIVISOR_STOP_VAL_2 0x01
|
||||
#define IT_SCR_SCDR_DIVISOR_STOP_VAL_3 0x7F
|
||||
|
||||
// IT8172 DMA
|
||||
#define IT_DMAC_BASE 0x16000
|
||||
#define IT_DMAC_BCAR0 0x00
|
||||
#define IT_DMAC_BCAR1 0x04
|
||||
#define IT_DMAC_BCAR2 0x08
|
||||
#define IT_DMAC_BCAR3 0x0C
|
||||
#define IT_DMAC_BCCR0 0x02
|
||||
#define IT_DMAC_BCCR1 0x06
|
||||
#define IT_DMAC_BCCR2 0x0a
|
||||
#define IT_DMAC_BCCR3 0x0e
|
||||
#define IT_DMAC_CR 0x10
|
||||
#define IT_DMAC_SR 0x12
|
||||
#define IT_DMAC_ESR 0x13
|
||||
#define IT_DMAC_RQR 0x14
|
||||
#define IT_DMAC_MR 0x16
|
||||
#define IT_DMAC_EMR 0x17
|
||||
#define IT_DMAC_MKR 0x18
|
||||
#define IT_DMAC_PAR0 0x20
|
||||
#define IT_DMAC_PAR1 0x22
|
||||
#define IT_DMAC_PAR2 0x24
|
||||
#define IT_DMAC_PAR3 0x26
|
||||
|
||||
// IT8172 IDE
|
||||
#define IT_IDE_BASE 0x17800
|
||||
#define IT_IDE_STATUS 0x1F7
|
||||
|
||||
// IT8172 Audio Controller
|
||||
#define IT_AC_BASE 0x17000
|
||||
#define IT_AC_PCMOV 0x00
|
||||
#define IT_AC_FMOV 0x02
|
||||
#define IT_AC_I2SV 0x04
|
||||
#define IT_AC_DRSS 0x06
|
||||
#define IT_AC_PCC 0x08
|
||||
#define IT_AC_PCDL 0x0A
|
||||
#define IT_AC_PCB1STA 0x0C
|
||||
#define IT_AC_PCB2STA 0x10
|
||||
#define IT_AC_CAPCC 0x14
|
||||
#define IT_AC_CAPCDL 0x16
|
||||
#define IT_AC_CAPB1STA 0x18
|
||||
#define IT_AC_CAPB2STA 0x1C
|
||||
#define IT_AC_CODECC 0x22
|
||||
#define IT_AC_I2SMC 0x24
|
||||
#define IT_AC_VS 0x26
|
||||
#define IT_AC_SRCS 0x28
|
||||
#define IT_AC_CIRCP 0x2A
|
||||
#define IT_AC_CIRDP 0x2C
|
||||
#define IT_AC_TM 0x4A
|
||||
#define IT_AC_PFDP 0x4C
|
||||
#define IT_AC_GC 0x54
|
||||
#define IT_AC_IMC 0x56
|
||||
#define IT_AC_ISC 0x5B
|
||||
#define IT_AC_OPL3SR 0x68
|
||||
#define IT_AC_OPL3DWDR 0x69
|
||||
#define IT_AC_OPL3AB1W 0x6A
|
||||
#define IT_AC_OPL3DW 0x6B
|
||||
#define IT_AC_BPDC 0x70
|
||||
|
||||
|
||||
// IT8172 Timer
|
||||
#define IT_TIMER_BASE 0x10800
|
||||
#define TIMER_TCVR0 0x00
|
||||
#define TIMER_TRVR0 0x02
|
||||
#define TIMER_TCR0 0x04
|
||||
#define TIMER_TIRR 0x06
|
||||
#define TIMER_TCVR1 0x08
|
||||
#define TIMER_TRVR1 0x0A
|
||||
#define TIMER_TCR1 0x0C
|
||||
#define TIMER_TIDR 0x0E
|
||||
|
||||
|
||||
#define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
|
||||
#define IT_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs))
|
||||
|
||||
#define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
|
||||
#define IT_IO_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
|
||||
|
||||
#define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
|
||||
#define IT_IO_READ16(ofs, data) data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
|
||||
|
||||
#endif
|
||||
@@ -1,140 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* IT8172 Consumer IR port defines.
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#define NUM_CIR_PORTS 2
|
||||
|
||||
/* Master Control Register */
|
||||
#define CIR_RESET 0x1
|
||||
#define CIR_FIFO_CLEAR 0x2
|
||||
#define CIR_SET_FIFO_TL(x) (((x)&0x3)<<2)
|
||||
#define CIR_ILE 0x10
|
||||
#define CIR_ILSEL 0x20
|
||||
|
||||
/* Interrupt Enable Register */
|
||||
#define CIR_TLDLIE 0x1
|
||||
#define CIR_RDAIE 0x2
|
||||
#define CIR_RFOIE 0x4
|
||||
#define CIR_IEC 0x80
|
||||
|
||||
/* Interrupt Identification Register */
|
||||
#define CIR_TLDLI 0x1
|
||||
#define CIR_RDAI 0x2
|
||||
#define CIR_RFOI 0x4
|
||||
#define CIR_NIP 0x80
|
||||
|
||||
/* Carrier Frequency Register */
|
||||
#define CIR_SET_CF(x) ((x)&0x1f)
|
||||
#define CFQ_38_480 0xB /* 38 KHz low, 480 KHz high */
|
||||
#define CIR_HCFS 0x20
|
||||
#define CIR_SET_HS(x) (((x)&0x1)<<5)
|
||||
|
||||
|
||||
/* Receiver Control Register */
|
||||
#define CIR_SET_RXDCR(x) ((x)&0x7)
|
||||
#define CIR_RXACT 0x8
|
||||
#define CIR_RXEND 0x10
|
||||
#define CIR_RDWOS 0x20
|
||||
#define CIR_SET_RDWOS(x) (((x)&0x1)<<5)
|
||||
#define CIR_RXEN 0x80
|
||||
|
||||
/* Transmitter Control Register */
|
||||
#define CIR_SET_TXMPW(x) ((x)&0x7)
|
||||
#define CIR_SET_TXMPM(x) (((x)&0x3)<<3)
|
||||
#define CIR_TXENDF 0x20
|
||||
#define CIR_TXRLE 0x40
|
||||
|
||||
/* Receiver FIFO Status Register */
|
||||
#define CIR_RXFBC_MASK 0x3f
|
||||
#define CIR_RXFTO 0x80
|
||||
|
||||
/* Wakeup Code Length Register */
|
||||
#define CIR_SET_WCL ((x)&0x3f)
|
||||
#define CIR_WCL_MASK(x) ((x)&0x3f)
|
||||
|
||||
/* Wakeup Power Control/Status Register */
|
||||
#define CIR_BTMON 0x2
|
||||
#define CIR_CIRON 0x4
|
||||
#define CIR_RCRST 0x10
|
||||
#define CIR_WCRST 0x20
|
||||
|
||||
struct cir_port {
|
||||
int port;
|
||||
unsigned short baud_rate;
|
||||
unsigned char fifo_tl;
|
||||
unsigned char cfq;
|
||||
unsigned char hcfs;
|
||||
unsigned char rdwos;
|
||||
unsigned char rxdcr;
|
||||
};
|
||||
|
||||
struct it8172_cir_regs {
|
||||
unsigned char dr; /* data */
|
||||
char pad;
|
||||
unsigned char mstcr; /* master control */
|
||||
char pad1;
|
||||
unsigned char ier; /* interrupt enable */
|
||||
char pad2;
|
||||
unsigned char iir; /* interrupt identification */
|
||||
char pad3;
|
||||
unsigned char cfr; /* carrier frequency */
|
||||
char pad4;
|
||||
unsigned char rcr; /* receiver control */
|
||||
char pad5;
|
||||
unsigned char tcr; /* transmitter control */
|
||||
char pad6;
|
||||
char pad7;
|
||||
char pad8;
|
||||
unsigned char bdlr; /* baud rate divisor low byte */
|
||||
char pad9;
|
||||
unsigned char bdhr; /* baud rate divisor high byte */
|
||||
char pad10;
|
||||
unsigned char tfsr; /* tx fifo byte count */
|
||||
char pad11;
|
||||
unsigned char rfsr; /* rx fifo status */
|
||||
char pad12;
|
||||
unsigned char wcl; /* wakeup code length */
|
||||
char pad13;
|
||||
unsigned char wcr; /* wakeup code read/write */
|
||||
char pad14;
|
||||
unsigned char wps; /* wakeup power control/status */
|
||||
};
|
||||
|
||||
int cir_port_init(struct cir_port *cir);
|
||||
extern void clear_fifo(struct cir_port *cir);
|
||||
extern void enable_receiver(struct cir_port *cir);
|
||||
extern void disable_receiver(struct cir_port *cir);
|
||||
extern void enable_rx_demodulation(struct cir_port *cir);
|
||||
extern void disable_rx_demodulation(struct cir_port *cir);
|
||||
extern void set_rx_active(struct cir_port *cir);
|
||||
extern void int_enable(struct cir_port *cir);
|
||||
extern void rx_int_enable(struct cir_port *cir);
|
||||
extern char get_int_status(struct cir_port *cir);
|
||||
extern int cir_get_rx_count(struct cir_port *cir);
|
||||
extern char cir_read_data(struct cir_port *cir);
|
||||
@@ -1,38 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Function prototypes for low level uart routines to
|
||||
* directly access a 16550 uart.
|
||||
*
|
||||
* Copyright 2000 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
extern void putch(const unsigned char c);
|
||||
extern void puts(unsigned char *cp);
|
||||
extern void fputs(unsigned char *cp);
|
||||
extern void put64(uint64_t ul);
|
||||
extern void put32(unsigned u);
|
||||
@@ -1,144 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* ITE 8172 Interrupt Numbering
|
||||
*
|
||||
* Copyright 2000 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ITEINT_H
|
||||
#define _MIPS_ITEINT_H
|
||||
|
||||
/*
|
||||
* Here's the "strategy":
|
||||
* We number the LPC serial irqs from 0 to 15,
|
||||
* the local bus irqs from 16 to 31,
|
||||
* the pci dev register interrupts from 32 to 47,
|
||||
* and the non-maskable ints from 48 to 53.
|
||||
*/
|
||||
|
||||
#define IT8172_LPC_IRQ_BASE 0 /* first LPC int number */
|
||||
#define IT8172_SERIRQ_0 (IT8172_LPC_IRQ_BASE + 0)
|
||||
#define IT8172_SERIRQ_1 (IT8172_LPC_IRQ_BASE + 1)
|
||||
#define IT8172_SERIRQ_2 (IT8172_LPC_IRQ_BASE + 2)
|
||||
#define IT8172_SERIRQ_3 (IT8172_LPC_IRQ_BASE + 3)
|
||||
#define IT8172_SERIRQ_4 (IT8172_LPC_IRQ_BASE + 4)
|
||||
#define IT8172_SERIRQ_5 (IT8172_LPC_IRQ_BASE + 5)
|
||||
#define IT8172_SERIRQ_6 (IT8172_LPC_IRQ_BASE + 6)
|
||||
#define IT8172_SERIRQ_7 (IT8172_LPC_IRQ_BASE + 7)
|
||||
#define IT8172_SERIRQ_8 (IT8172_LPC_IRQ_BASE + 8)
|
||||
#define IT8172_SERIRQ_9 (IT8172_LPC_IRQ_BASE + 9)
|
||||
#define IT8172_SERIRQ_10 (IT8172_LPC_IRQ_BASE + 10)
|
||||
#define IT8172_SERIRQ_11 (IT8172_LPC_IRQ_BASE + 11)
|
||||
#define IT8172_SERIRQ_12 (IT8172_LPC_IRQ_BASE + 12)
|
||||
#define IT8172_SERIRQ_13 (IT8172_LPC_IRQ_BASE + 13)
|
||||
#define IT8172_SERIRQ_14 (IT8172_LPC_IRQ_BASE + 14)
|
||||
#define IT8172_SERIRQ_15 (IT8172_LPC_IRQ_BASE + 15)
|
||||
|
||||
#define IT8172_LB_IRQ_BASE 16 /* first local bus int number */
|
||||
#define IT8172_PPR_IRQ (IT8172_LB_IRQ_BASE + 0) /* parallel port */
|
||||
#define IT8172_TIMER0_IRQ (IT8172_LB_IRQ_BASE + 1)
|
||||
#define IT8172_TIMER1_IRQ (IT8172_LB_IRQ_BASE + 2)
|
||||
#define IT8172_I2C_IRQ (IT8172_LB_IRQ_BASE + 3)
|
||||
#define IT8172_GPIO_IRQ (IT8172_LB_IRQ_BASE + 4)
|
||||
#define IT8172_CIR0_IRQ (IT8172_LB_IRQ_BASE + 5)
|
||||
#define IT8172_CIR1_IRQ (IT8172_LB_IRQ_BASE + 6)
|
||||
#define IT8172_UART_IRQ (IT8172_LB_IRQ_BASE + 7)
|
||||
#define IT8172_SCR0_IRQ (IT8172_LB_IRQ_BASE + 8)
|
||||
#define IT8172_SCR1_IRQ (IT8172_LB_IRQ_BASE + 9)
|
||||
#define IT8172_RTC_IRQ (IT8172_LB_IRQ_BASE + 10)
|
||||
#define IT8172_IOCHK_IRQ (IT8172_LB_IRQ_BASE + 11)
|
||||
/* 12 - 15 reserved */
|
||||
|
||||
/*
|
||||
* Note here that the pci dev registers includes bits for more than
|
||||
* just the pci devices.
|
||||
*/
|
||||
#define IT8172_PCI_DEV_IRQ_BASE 32 /* first pci dev irq */
|
||||
#define IT8172_AC97_IRQ (IT8172_PCI_DEV_IRQ_BASE + 0)
|
||||
#define IT8172_MC68K_IRQ (IT8172_PCI_DEV_IRQ_BASE + 1)
|
||||
#define IT8172_IDE_IRQ (IT8172_PCI_DEV_IRQ_BASE + 2)
|
||||
#define IT8172_USB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 3)
|
||||
#define IT8172_BRIDGE_MASTER_IRQ (IT8172_PCI_DEV_IRQ_BASE + 4)
|
||||
#define IT8172_BRIDGE_TARGET_IRQ (IT8172_PCI_DEV_IRQ_BASE + 5)
|
||||
#define IT8172_PCI_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 6)
|
||||
#define IT8172_PCI_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 7)
|
||||
#define IT8172_PCI_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 8)
|
||||
#define IT8172_PCI_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 9)
|
||||
#define IT8172_S_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 10)
|
||||
#define IT8172_S_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 11)
|
||||
#define IT8172_S_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 12)
|
||||
#define IT8172_S_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 13)
|
||||
#define IT8172_CDMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 14)
|
||||
#define IT8172_DMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 15)
|
||||
|
||||
#define IT8172_NMI_IRQ_BASE 48
|
||||
#define IT8172_SER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 0)
|
||||
#define IT8172_PCI_NMI_IRQ (IT8172_NMI_IRQ_BASE + 1)
|
||||
#define IT8172_RTC_NMI_IRQ (IT8172_NMI_IRQ_BASE + 2)
|
||||
#define IT8172_CPUIF_NMI_IRQ (IT8172_NMI_IRQ_BASE + 3)
|
||||
#define IT8172_PMER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 4)
|
||||
#define IT8172_POWER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 5)
|
||||
|
||||
#define IT8172_LAST_IRQ (IT8172_POWER_NMI_IRQ)
|
||||
/* Finally, let's move over here the mips cpu timer interrupt.
|
||||
*/
|
||||
#define MIPS_CPU_TIMER_IRQ (NR_IRQS-1)
|
||||
|
||||
/*
|
||||
* IT8172 Interrupt Controller Registers
|
||||
*/
|
||||
struct it8172_intc_regs {
|
||||
volatile unsigned short lb_req; /* offset 0 */
|
||||
volatile unsigned short lb_mask;
|
||||
volatile unsigned short lb_trigger;
|
||||
volatile unsigned short lb_level;
|
||||
unsigned char pad0[8];
|
||||
|
||||
volatile unsigned short lpc_req; /* offset 0x10 */
|
||||
volatile unsigned short lpc_mask;
|
||||
volatile unsigned short lpc_trigger;
|
||||
volatile unsigned short lpc_level;
|
||||
unsigned char pad1[8];
|
||||
|
||||
volatile unsigned short pci_req; /* offset 0x20 */
|
||||
volatile unsigned short pci_mask;
|
||||
volatile unsigned short pci_trigger;
|
||||
volatile unsigned short pci_level;
|
||||
unsigned char pad2[8];
|
||||
|
||||
volatile unsigned short nmi_req; /* offset 0x30 */
|
||||
volatile unsigned short nmi_mask;
|
||||
volatile unsigned short nmi_trigger;
|
||||
volatile unsigned short nmi_level;
|
||||
unsigned char pad3[6];
|
||||
|
||||
volatile unsigned short nmi_redir; /* offset 0x3E */
|
||||
unsigned char pad4[0xBE];
|
||||
|
||||
volatile unsigned short intstatus; /* offset 0xFE */
|
||||
};
|
||||
|
||||
#endif /* _MIPS_ITEINT_H */
|
||||
@@ -1,108 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* IT8172 system controller specific pci defines.
|
||||
*
|
||||
* Copyright 2000 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef _8172PCI_H_
|
||||
#define _8172PCI_H_
|
||||
|
||||
// PCI configuration space Type0
|
||||
#define PCI_IDREG 0x00
|
||||
#define PCI_CMDSTSREG 0x04
|
||||
#define PCI_CLASSREG 0x08
|
||||
#define PCI_BHLCREG 0x0C
|
||||
#define PCI_BASE1REG 0x10
|
||||
#define PCI_BASE2REG 0x14
|
||||
#define PCI_BASE3REG 0x18
|
||||
#define PCI_BASE4REG 0x1C
|
||||
#define PCI_BASE5REG 0x20
|
||||
#define PCI_BASE6REG 0x24
|
||||
#define PCI_ROMBASEREG 0x30
|
||||
#define PCI_INTRREG 0x3C
|
||||
|
||||
// PCI configuration space Type1
|
||||
#define PCI_BUSNOREG 0x18
|
||||
|
||||
#define IT_PCI_VENDORID(x) ((x) & 0xFFFF)
|
||||
#define IT_PCI_DEVICEID(x) (((x)>>16) & 0xFFFF)
|
||||
|
||||
// Command register
|
||||
#define PCI_CMD_IOEN 0x00000001
|
||||
#define PCI_CMD_MEMEN 0x00000002
|
||||
#define PCI_CMD_BUSMASTER 0x00000004
|
||||
#define PCI_CMD_SPCYCLE 0x00000008
|
||||
#define PCI_CMD_WRINV 0x00000010
|
||||
#define PCI_CMD_VGASNOOP 0x00000020
|
||||
#define PCI_CMD_PERR 0x00000040
|
||||
#define PCI_CMD_WAITCTRL 0x00000080
|
||||
#define PCI_CMD_SERR 0x00000100
|
||||
#define PCI_CMD_FAST_BACKTOBACK 0x00000200
|
||||
|
||||
// Status register
|
||||
#define PCI_STS_66MHZ 0x00200000
|
||||
#define PCI_STS_SUPPORT_UDF 0x00400000
|
||||
#define PCI_STS_FAST_BACKTOBACK 0x00800000
|
||||
#define PCI_STS_DATA_PERR 0x01000000
|
||||
#define PCI_STS_DEVSEL0 0x02000000
|
||||
#define PCI_STS_DEVSEL1 0x04000000
|
||||
#define PCI_STS_SIG_TGTABORT 0x08000000
|
||||
#define PCI_STS_RCV_TGTABORT 0x10000000
|
||||
#define PCI_STS_RCV_MSTABORT 0x20000000
|
||||
#define PCI_STS_SYSERR 0x40000000
|
||||
#define PCI_STS_DETCT_PERR 0x80000000
|
||||
|
||||
#define IT_PCI_CLASS(x) (((x)>>24) & 0xFF)
|
||||
#define IT_PCI_SUBCLASS(x) (((x)>>16) & 0xFF)
|
||||
#define IT_PCI_INTERFACE(x) (((x)>>8) & 0xFF)
|
||||
#define IT_PCI_REVISION(x) ((x) & 0xFF)
|
||||
|
||||
// PCI class code
|
||||
#define PCI_CLASS_BRIDGE 0x06
|
||||
|
||||
// bridge subclass
|
||||
#define PCI_SUBCLASS_BRIDGE_HOST 0x00
|
||||
#define PCI_SUBCLASS_BRIDGE_PCI 0x04
|
||||
|
||||
// BHLCREG
|
||||
#define IT_PCI_BIST(x) (((x)>>24) & 0xFF)
|
||||
#define IT_PCI_HEADERTYPE(x) (((x)>>16) & 0xFF)
|
||||
#define IT_PCI_LATENCYTIMER(x) (((x)>>8) & 0xFF)
|
||||
#define IT_PCI_CACHELINESIZE(x) ((x) & 0xFF)
|
||||
|
||||
#define PCI_MULTIFUNC 0x80
|
||||
|
||||
// INTRREG
|
||||
#define IT_PCI_MAXLAT(x) (((x)>>24) & 0xFF)
|
||||
#define IT_PCI_MINGNT(x) (((x)>>16) & 0xFF)
|
||||
#define IT_PCI_INTRPIN(x) (((x)>>8) & 0xFF)
|
||||
#define IT_PCI_INTRLINE(x) ((x) & 0xFF)
|
||||
|
||||
#define PCI_VENDOR_NEC 0x1033
|
||||
#define PCI_VENDOR_DEC 0x1101
|
||||
|
||||
#endif // _8172PCI_H_
|
||||
@@ -1,28 +0,0 @@
|
||||
|
||||
#ifndef __IT8712_H__
|
||||
#define __IT8712_H__
|
||||
|
||||
#define LPC_BASE_ADDR 0x14000000
|
||||
|
||||
// MB PnP configuration register
|
||||
#define LPC_KEY_ADDR 0x1400002E
|
||||
#define LPC_DATA_ADDR 0x1400002F
|
||||
|
||||
// Device LDN
|
||||
#define LDN_SERIAL1 0x01
|
||||
#define LDN_SERIAL2 0x02
|
||||
#define LDN_PARALLEL 0x03
|
||||
#define LDN_KEYBOARD 0x05
|
||||
#define LDN_MOUSE 0x06
|
||||
|
||||
#define IT8712_UART1_PORT 0x3F8
|
||||
#define IT8712_UART2_PORT 0x2F8
|
||||
|
||||
#ifndef ASM_ONLY
|
||||
|
||||
void LPCSetConfig(char LdnNumber, char Index, char data);
|
||||
char LPCGetConfig(char LdnNumber, char Index);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -44,9 +44,8 @@ struct pt_regs {
|
||||
unsigned long cp0_epc;
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
unsigned long cp0_tcstatus;
|
||||
unsigned long smtc_pad;
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
};
|
||||
} __attribute__ ((aligned (8)));
|
||||
|
||||
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
|
||||
#define PTRACE_GETREGS 12
|
||||
|
||||
@@ -69,38 +69,6 @@
|
||||
#define EV64120_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_ITE8172
|
||||
#include <asm/it8172/it8172.h>
|
||||
#include <asm/it8172/it8172_int.h>
|
||||
#include <asm/it8712.h>
|
||||
#define ITE_SERIAL_PORT_DEFNS \
|
||||
{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
|
||||
.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
|
||||
{ .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
|
||||
.irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
|
||||
/* Smart Card Reader 0 */ \
|
||||
{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
|
||||
.irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
|
||||
/* Smart Card Reader 1 */ \
|
||||
{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
|
||||
.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 },
|
||||
#else
|
||||
#define ITE_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_IVR
|
||||
#include <asm/it8172/it8172.h>
|
||||
#include <asm/it8172/it8172_int.h>
|
||||
#define IVR_SERIAL_PORT_DEFNS \
|
||||
{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
|
||||
.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
|
||||
/* Smart Card Reader 1 */ \
|
||||
{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
|
||||
.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 },
|
||||
#else
|
||||
#define IVR_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
|
||||
#define STD_SERIAL_PORT_DEFNS \
|
||||
/* UART CLK PORT IRQ FLAGS */ \
|
||||
@@ -240,8 +208,6 @@
|
||||
DDB5477_SERIAL_PORT_DEFNS \
|
||||
EV64120_SERIAL_PORT_DEFNS \
|
||||
IP32_SERIAL_PORT_DEFNS \
|
||||
ITE_SERIAL_PORT_DEFNS \
|
||||
IVR_SERIAL_PORT_DEFNS \
|
||||
JAZZ_SERIAL_PORT_DEFNS \
|
||||
STD_SERIAL_PORT_DEFNS \
|
||||
MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
|
||||
|
||||
@@ -1,66 +0,0 @@
|
||||
/*
|
||||
* FILE NAME ite_gpio.h
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Generic gpio.
|
||||
*
|
||||
* Author: MontaVista Software, Inc. <source@mvista.com>
|
||||
* Hai-Pao Fan <haipao@mvista.com>
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __ITE_GPIO_H
|
||||
#define __ITE_GPIO_H
|
||||
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
struct ite_gpio_ioctl_data {
|
||||
__u32 device;
|
||||
__u32 mask;
|
||||
__u32 data;
|
||||
};
|
||||
|
||||
#define ITE_GPIO_IOCTL_BASE 'Z'
|
||||
|
||||
#define ITE_GPIO_IN _IOWR(ITE_GPIO_IOCTL_BASE, 0, struct ite_gpio_ioctl_data)
|
||||
#define ITE_GPIO_OUT _IOW (ITE_GPIO_IOCTL_BASE, 1, struct ite_gpio_ioctl_data)
|
||||
#define ITE_GPIO_INT_CTRL _IOW (ITE_GPIO_IOCTL_BASE, 2, struct ite_gpio_ioctl_data)
|
||||
#define ITE_GPIO_IN_STATUS _IOW (ITE_GPIO_IOCTL_BASE, 3, struct ite_gpio_ioctl_data)
|
||||
#define ITE_GPIO_OUT_STATUS _IOW (ITE_GPIO_IOCTL_BASE, 4, struct ite_gpio_ioctl_data)
|
||||
#define ITE_GPIO_GEN_CTRL _IOW (ITE_GPIO_IOCTL_BASE, 5, struct ite_gpio_ioctl_data)
|
||||
#define ITE_GPIO_INT_WAIT _IOW (ITE_GPIO_IOCTL_BASE, 6, struct ite_gpio_ioctl_data)
|
||||
|
||||
#define ITE_GPIO_PORTA 0x01
|
||||
#define ITE_GPIO_PORTB 0x02
|
||||
#define ITE_GPIO_PORTC 0x04
|
||||
|
||||
extern int ite_gpio_in(__u32 device, __u32 mask, volatile __u32 *data);
|
||||
extern int ite_gpio_out(__u32 device, __u32 mask, __u32 data);
|
||||
extern int ite_gpio_int_ctrl(__u32 device, __u32 mask, __u32 data);
|
||||
extern int ite_gpio_in_status(__u32 device, __u32 mask, volatile __u32 *data);
|
||||
extern int ite_gpio_out_status(__u32 device, __u32 mask, __u32 data);
|
||||
extern int ite_gpio_gen_ctrl(__u32 device, __u32 mask, __u32 data);
|
||||
extern int ite_gpio_int_wait(__u32 device, __u32 mask, __u32 data);
|
||||
|
||||
#endif
|
||||
@@ -1615,8 +1615,6 @@
|
||||
#define PCI_VENDOR_ID_ROCKWELL 0x127A
|
||||
|
||||
#define PCI_VENDOR_ID_ITE 0x1283
|
||||
#define PCI_DEVICE_ID_ITE_IT8172G 0x8172
|
||||
#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
|
||||
#define PCI_DEVICE_ID_ITE_8211 0x8211
|
||||
#define PCI_DEVICE_ID_ITE_8212 0x8212
|
||||
#define PCI_DEVICE_ID_ITE_8872 0x8872
|
||||
@@ -1883,6 +1881,8 @@
|
||||
#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400
|
||||
#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402
|
||||
|
||||
#define PCI_VENDOR_ID_SIPACKETS 0x14d9
|
||||
#define PCI_DEVICE_ID_SP1011 0x0010
|
||||
|
||||
#define PCI_VENDOR_ID_AFAVLAB 0x14db
|
||||
#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180
|
||||
@@ -1997,6 +1997,7 @@
|
||||
#define PCI_DEVICE_ID_FARSITE_TE1C 0x1612
|
||||
|
||||
#define PCI_VENDOR_ID_SIBYTE 0x166d
|
||||
#define PCI_DEVICE_ID_BCM1250_PCI 0x0001
|
||||
#define PCI_DEVICE_ID_BCM1250_HT 0x0002
|
||||
|
||||
#define PCI_VENDOR_ID_NETCELL 0x169c
|
||||
|
||||
Reference in New Issue
Block a user