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Catalin Marinas
4ab5f8ec7d
Patch series "mm, dma, arm64: Reduce ARCH_KMALLOC_MINALIGN to 8", v7. A series reducing the kmalloc() minimum alignment on arm64 to 8 (from 128). This patch (of 17): In preparation for supporting a kmalloc() minimum alignment smaller than the arch DMA alignment, decouple the two definitions. This requires that either the kmalloc() caches are aligned to a (run-time) cache-line size or the DMA API bounces unaligned kmalloc() allocations. Subsequent patches will implement both options. After this patch, ARCH_DMA_MINALIGN is expected to be used in static alignment annotations and defined by an architecture to be the maximum alignment for all supported configurations/SoCs in a single Image. Architectures opting in to a smaller ARCH_KMALLOC_MINALIGN will need to define its value in the arch headers. Since ARCH_DMA_MINALIGN is now always defined, adjust the #ifdef in dma_get_cache_alignment() so that there is no change for architectures not requiring a minimum DMA alignment. Link: https://lkml.kernel.org/r/[email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Catalin Marinas <[email protected]> Tested-by: Isaac J. Manjarres <[email protected]> Cc: Vlastimil Babka <[email protected]> Cc: Christoph Hellwig <[email protected]> Cc: Robin Murphy <[email protected]> Cc: Alasdair Kergon <[email protected]> Cc: Ard Biesheuvel <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: Herbert Xu <[email protected]> Cc: Joerg Roedel <[email protected]> Cc: Jonathan Cameron <[email protected]> Cc: Marc Zyngier <[email protected]> Cc: Mark Brown <[email protected]> Cc: Mike Snitzer <[email protected]> Cc: Rafael J. Wysocki <[email protected]> Cc: Saravana Kannan <[email protected]> Cc: Will Deacon <[email protected]> Cc: Jerry Snitselaar <[email protected]> Cc: Jonathan Cameron <[email protected]> Cc: Lars-Peter Clausen <[email protected]> Cc: Logan Gunthorpe <[email protected]> Signed-off-by: Andrew Morton <[email protected]>
108 lines
3.0 KiB
C
108 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_CACHE_H
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#define __LINUX_CACHE_H
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#include <uapi/linux/kernel.h>
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#include <asm/cache.h>
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#ifndef L1_CACHE_ALIGN
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#define L1_CACHE_ALIGN(x) __ALIGN_KERNEL(x, L1_CACHE_BYTES)
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#endif
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#ifndef SMP_CACHE_BYTES
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#endif
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/*
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* __read_mostly is used to keep rarely changing variables out of frequently
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* updated cachelines. Its use should be reserved for data that is used
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* frequently in hot paths. Performance traces can help decide when to use
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* this. You want __read_mostly data to be tightly packed, so that in the
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* best case multiple frequently read variables for a hot path will be next
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* to each other in order to reduce the number of cachelines needed to
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* execute a critical path. We should be mindful and selective of its use.
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* ie: if you're going to use it please supply a *good* justification in your
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* commit log
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*/
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#ifndef __read_mostly
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#define __read_mostly
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#endif
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/*
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* __ro_after_init is used to mark things that are read-only after init (i.e.
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* after mark_rodata_ro() has been called). These are effectively read-only,
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* but may get written to during init, so can't live in .rodata (via "const").
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*/
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#ifndef __ro_after_init
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#define __ro_after_init __section(".data..ro_after_init")
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#endif
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#ifndef ____cacheline_aligned
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#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
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#endif
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#ifndef ____cacheline_aligned_in_smp
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#ifdef CONFIG_SMP
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#define ____cacheline_aligned_in_smp ____cacheline_aligned
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#else
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#define ____cacheline_aligned_in_smp
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#endif /* CONFIG_SMP */
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#endif
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#ifndef __cacheline_aligned
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#define __cacheline_aligned \
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__attribute__((__aligned__(SMP_CACHE_BYTES), \
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__section__(".data..cacheline_aligned")))
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#endif /* __cacheline_aligned */
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#ifndef __cacheline_aligned_in_smp
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#ifdef CONFIG_SMP
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#define __cacheline_aligned_in_smp __cacheline_aligned
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#else
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#define __cacheline_aligned_in_smp
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#endif /* CONFIG_SMP */
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#endif
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/*
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* The maximum alignment needed for some critical structures
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* These could be inter-node cacheline sizes/L3 cacheline
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* size etc. Define this in asm/cache.h for your arch
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*/
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#ifndef INTERNODE_CACHE_SHIFT
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#define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT
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#endif
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#if !defined(____cacheline_internodealigned_in_smp)
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#if defined(CONFIG_SMP)
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#define ____cacheline_internodealigned_in_smp \
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__attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))
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#else
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#define ____cacheline_internodealigned_in_smp
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#endif
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#endif
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#ifndef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
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#define cache_line_size() L1_CACHE_BYTES
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#endif
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/*
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* Helper to add padding within a struct to ensure data fall into separate
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* cachelines.
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*/
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#if defined(CONFIG_SMP)
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struct cacheline_padding {
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char x[0];
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} ____cacheline_internodealigned_in_smp;
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#define CACHELINE_PADDING(name) struct cacheline_padding name
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#else
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#define CACHELINE_PADDING(name)
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#endif
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#ifdef ARCH_DMA_MINALIGN
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#define ARCH_HAS_DMA_MINALIGN
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#else
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#define ARCH_DMA_MINALIGN __alignof__(unsigned long long)
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#endif
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#endif /* __LINUX_CACHE_H */
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