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Adam Ford
89691775f5
The DPHY timings are currently hard coded. Since the input clock can be variable, the phy timings need to be variable too. To facilitate this, we need to cache the hs_clock based on what is generated from the PLL. The phy_mipi_dphy_get_default_config_for_hsclk function configures the DPHY timings in pico-seconds, and a small macro converts those timings into clock cycles based on the hs_clk. Signed-off-by: Adam Ford <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Tested-by: Chen-Yu Tsai <[email protected]> Tested-by: Frieder Schrempf <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]> Tested-by: Michael Walle <[email protected]> Tested-by: Marek Szyprowski <[email protected]> Reviewed-by: Jagan Teki <[email protected]> Tested-by: Jagan Teki <[email protected]> # imx8mm-icore Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]