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Atish Patra
3a9f66cb25
The RISC-V hypervisor specification doesn't have any virtual timer feature. Due to this, the guest VCPU timer will be programmed via SBI calls. The host will use a separate hrtimer event for each guest VCPU to provide timer functionality. We inject a virtual timer interrupt to the guest VCPU whenever the guest VCPU hrtimer event expires. This patch adds guest VCPU timer implementation along with ONE_REG interface to access VCPU timer state from user space. Signed-off-by: Atish Patra <[email protected]> Signed-off-by: Anup Patel <[email protected]> Acked-by: Paolo Bonzini <[email protected]> Reviewed-by: Paolo Bonzini <[email protected]> Acked-by: Daniel Lezcano <[email protected]> Acked-by: Palmer Dabbelt <[email protected]>
17 lines
316 B
C
17 lines
316 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Atish Patra <[email protected]>
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*/
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#ifndef __TIMER_RISCV_H
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#define __TIMER_RISCV_H
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#include <linux/types.h>
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extern void riscv_cs_get_mult_shift(u32 *mult, u32 *shift);
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#endif
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