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ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition

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This patch adds a macro to define the GPR3 MIPI muxing control register field
shift bits.

Signed-off-by: Liu Ying <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
This commit is contained in:
Liu Ying authored and Shawn Guo committed 2015-03-02 20:51:55 +08:00
1 parent af321d2e32
commit 5f80e19081
1 file changed
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include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
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@@ -207,6 +207,7 @@
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6)
#define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4
#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4)