drm/amd/display: Move MAX_TMDS_CLOCK define to header

Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
This commit is contained in:
Harry Wentland authored and Alex Deucher committed 2018-03-07 16:27:14 -05:00
1 parent 0c813535ee
commit 855b5cba0d
4 files changed
+5 -15

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@@ -1360,9 +1360,6 @@ bool dc_is_stream_scaling_unchanged(
return true;
}
/* Maximum TMDS single link pixel clock 165MHz */
#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
static void update_stream_engine_usage(
struct resource_context *res_ctx,
const struct resource_pool *pool,
@@ -82,13 +82,6 @@
#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
#define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
#define TMDS_MIN_PIXEL_CLOCK 25000
/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
#define TMDS_MAX_PIXEL_CLOCK 165000
/* For current ASICs pixel clock - 600MHz */
#define MAX_ENCODER_CLOCK 600000
enum {
DP_MST_UPDATE_MAX_RETRY = 50
};
@@ -419,11 +419,6 @@ struct bios_event_info {
bool backlight_changed;
};
enum {
HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
};
/*
* DFS-bypass flag
*/
@@ -26,6 +26,11 @@
#ifndef __DC_SIGNAL_TYPES_H__
#define __DC_SIGNAL_TYPES_H__
/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
#define TMDS_MIN_PIXEL_CLOCK 25000
/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
#define TMDS_MAX_PIXEL_CLOCK 165000
enum signal_type {
SIGNAL_TYPE_NONE = 0L, /* no signal */
SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0),