The 'num-chipselects' property is not a valid property according
to Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt, so
let's remove it.
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
On the imx6qdl-zii-rdu2 board the RTC functionality is provided via
a DS1341 RTC connected via I2C bus, so we can safely disable the internal
one.
Reported-by: Chris Healy <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
Tested-by: Chris Healy <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
According to Documentation/devicetree/bindings/rtc/rtc-ds1307.txt the
original compatible "maxim,ds1341" is not a valid entry.
Switch to the documented "dallas,ds1341" compatible.
Reported-by: Chris Healy <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
Tested-by: Chris Healy <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first, so use the nvmem-cells binding instead.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
dtc has new checks for SPI buses. Fix the warnings in node names and
unit-addresses.
There's over 100 warnings for FSL boards, a few examples:
arch/arm/boot/dts/imx28-duckbill-2-spi.dtb: Warning (spi_bus_bridge): /apb@80000000/apbh@80000000/ssp@80014000: node name for SPI buses should be 'spi'
arch/arm/boot/dts/imx53-ppd.dtb: Warning (spi_bus_bridge): /soc/aips@50000000/spba@50000000/ecspi@50010000: node name for SPI buses should be 'spi'
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dtb: Warning (spi_bus_reg): /soc/aips-bus@2000000/spba-bus@2000000/spi@2014000/mcp251x@1: SPI bus unit address format error, expected "0"
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: Li Yang <[email protected]>
Cc: Stefan Agner <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Acked-by: Stefan Agner <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
No SDIO devices are connected to these ports, so pass the 'no-sdio'
property.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Andrey Smirnov <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
imx51-zii-scu2-mezz has an external watchdog in the environment
microcontroller, so disable the internal one.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Andrey Smirnov <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
imx51-zii-scu2-mezz does not have any video encoding/decoding needs,
so disable the VPU.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Andrey Smirnov <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
imx51-zii-scu3-esb does not have any video encoding/decoding needs,
so disable the VPU.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Andrey Smirnov <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Update VDD_SOC voltage to 1.25V for 900MHz operating point
according to datasheet Rev. 1.3, 08/2018, 25mV is added to
the minimum allowed values to cover power supply ripple.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Sébastien Szymanski <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
This board, as well as some other boards with i.MX6 and a PMIC, uses a
"PMIC_STBY_REQ" line to notify the PMIC about a state change.
The PMIC is programmed for a specific state change before triggering the
line.
In this case, PMIC_STBY_REQ can be used for stand by, sleep
and power off modes.
Signed-off-by: Oleksij Rempel <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The pinctrl properties on the IOMUXC node get overwritten by the
carrier board level device tree, hence the pinctrl_reset_moci
pinctrl does not get applied.
Associate the pinctrl_reset_moci pinctrl with the PCIe node where
we also make use of the pin as a reset GPIO.
Since the pin is muxed as a GPIO by default not muxing it explicitly
worked fine in practise.
Signed-off-by: Stefan Agner <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
There is no need to keep the PMU disabled.
Enable it like it is done in the other i.MX dtsi files.
With this change applied we see:
[ 1.338866] hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The board typically has 2 populated SFF interfaces. The mv88e6xxx
driver currently supports SFF modules connected to ports 9 and 10 of
the mv88e6390. Add support for sff2, which is connected to port 9.
Signed-off-by: Russell King <[email protected]>
Signed-off-by: Andrew Lunn <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The switch has an SFF attached to port 5. Add the SFF device, the
pinmux for its GPIOs, and list the port in the switch configuration.
Signed-off-by: Andrew Lunn <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
NOR and IFC controller connectivity is big-endian.
So add big-endian field in nor device tree node allowing
IFC controller to read/write data from/to the flash correctly.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Acked-by: Li Yang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX6ULL is a lite version of i.MX6UL, its full name
is i.MX6 UltraLiteLite, NOT UlltraLite.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX6SLL has GPIO clock gates in CCM CCGR, add
clock property for GPIO driver to make sure all
GPIO banks work as expected.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Signals available on both i.MX6UL and i.MX6ULL should have the same name
because it is the case of all others common signals, it avoids to make
mistakes (use the wrong ones) and it makes writing device tree files
less complicated. For example:
imx6ul-imx6ull-board.dtsi:
...
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
>;
};
imx6ul-board.dts:
#include <imx6ul.dtsi>
#include <imx6ul-imx6ull-board.dtsi>
...
imx6ull-board.dts:
#include <imx6ull.dtsi>
#include <imx6ul-imx6ull-board.dtsi>
...
Without this patch, the imx6ull-board.dtb will use
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX instead of
MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX and the uart5 will be
misconfigured.
Signed-off-by: Sébastien Szymanski <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Setting a stdout-path in the .dtb is convenient because then the user
gets a serial console on the RS-232 connector without any extra effort
of figuring out the relevant 'console=' boot parameter.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The WaRP7 has one mikroBUS socket on the back to plug click boards.
This patch allows to interact with some of these
i2c modules (EEPROM, RTC and so on).
Signed-off-by: Pierre-Jean Texier <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The "EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation" is based on the 1.5 version
of the i.Core MX6 cpu module. The 1.5 version differs from the original one for
a few details, including the ethernet PHY interface clock provider.
With this commit, the ethernet interface works properly:
SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver
While before using the 1.5 version, ethernet failed to startup do to un-clocked
PHY interface:
fec 2188000.ethernet eth0: could not attach to PHY
Fixes: 3fe0883577 ("ARM: dts: imx6q: Add Engicam i.CoreM6 1.5 Quad/Dual MIPI starter kit support")
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Jacopo Mondi <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The 1.5 version of Engicam's i.Core MX6 CPU module features a different clock
provider for the ethernet's PHY interface. Adjust the FEC ptp clock to
reference CLK_ENET_REF clock source, and set SION bit of
MX6QDL_PAD_GPIO_16__ENET_REF_CLK to adjust the input path of that pin.
The newly introduced imx6ql-icore-1.5.dtsi allows to collect in a single
place differences between version '1.0' and '1.5' of the module.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Jacopo Mondi <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Move usdhc2 and gpmi along with pinctrl nodes on
imx6ul-isiot.dtsi from dts files and mark it as 'disabled'
and the relevant dts will enable the status as 'okay'
Signed-off-by: Jagan Teki <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Define the Messaging Unit (MU) for i.MX7 in the processor's dtsi.
The respective driver is added in the next commit.
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Oleksij Rempel <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The i.MX7ULP B0 chip has some pin changes for USB and VIU
module, update pinfunc header file accordingly.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The MC13892 Analog-to-Digital input pins (ADIN5-7) are exposed on the
imx51-babbage board.
Pass the "fsl,mc13xxx-uses-adc" property so that the MC13892 ADC
block can work.
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Add "gpio-ranges" property to establish connections between GPIOs
and PINs on i.MX6SLL pinctrl driver, for details, please refer to
Documentation/devicetree/bindings/gpio/gpio.txt of "gpio-ranges"
property.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Anson Huang