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Author SHA1 Message Date
Geert Uytterhoeven 36ff366033 clk: renesas: r8a779g0: Add PFC/GPIO clocks 
Add the module clocks used by the Pin Function Controller (PFC) and
General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4H
(R8A779G0) SoC.

Extracted from a larger patch in the BSP by Kazuya Mizuguchi.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/cc6a22f0ad49643e17b9921b27aa9cf0a3b8d57a.1662714852.git.geert+renesas@glider.be
 2022-09-18 14:43:51 +02:00
Geert Uytterhoeven e90eba2ecb clk: renesas: r8a779g0: Add I2C clocks 
Add the module clocks used by the I2C Bus Interfaces on the Renesas
R-Car V4H (R8A779G0) SoC.

Extracted from a larger patch in the BSP by Kazuya Mizuguchi.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/f4b94f37950f6e976b68d0b32c324fb026d8b696.1662714852.git.geert+renesas@glider.be
 2022-09-18 14:43:51 +02:00
Geert Uytterhoeven a4f8a6e60c clk: renesas: r8a779g0: Add watchdog clock 
Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4H (R8A779G0) SoC.

Extracted from a larger patch in the BSP by Kazuya Mizuguchi.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/a012e4449b976efbeaabebb983fa6cfc1b9329d3.1662714852.git.geert+renesas@glider.be
 2022-09-18 14:43:51 +02:00
Geert Uytterhoeven 7251ceb51a sysctl: Merge adjacent CONFIG_TREE_RCU blocks 
There are two adjacent sysctl entries protected by the same
CONFIG_TREE_RCU config symbol.  Merge them into a single block to
improve readability.

Use the more common "#ifdef" form while at it.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Paul E. McKenney <[email protected]>
Signed-off-by: Luis Chamberlain <[email protected]>
 2022-08-08 09:01:36 -07:00
Geert Uytterhoeven 4abb38595b dt-bindings: timer: renesas,cmt: Fix R-Car Gen4 fall-out 
Restore sort order (by family, followed by type).
Update the conditional sections specifying the number of interrupts.

Fixes: 525b296185 ("dt-bindings: timer: renesas,cmt: Add r8a779f0 and generic Gen4 CMT support")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/2e3863ae32e17d49f41111580f195dd34e2b769d.1658303544.git.geert+renesas@glider.be
Signed-off-by: Daniel Lezcano <[email protected]>
 2022-07-27 17:01:52 +02:00
Geert Uytterhoeven e76f4a6107 of: overlay: Simplify of_overlay_fdt_apply() tail 
It does not hurt to fill in the changeset id while the mutex is still
held.  After doing so, the function tails for the success and failure
cases become identical, so they can be unified.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Frank Rowand <[email protected]>
Tested-by: Frank Rowand <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/6a3357a8f7f29704350e3ffae768ee8a462b54d3.1657893306.git.geert+renesas@glider.be
 2022-07-19 15:56:48 -06:00
Geert Uytterhoeven e385b0ba6a of: overlay: Move devicetree_corrupt() check up 
There is no point in doing several preparatory steps in
of_overlay_fdt_apply(), only to see of_overlay_apply() return early
because of a corrupt device tree.

Move the check for a corrupt device tree from of_overlay_apply() to
of_overlay_fdt_apply(), to check for this as early as possible.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Frank Rowand <[email protected]>
Tested-by: Frank Rowand <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/c91ce7112eb5167ea46a43d8a980e76b920010ba.1657893306.git.geert+renesas@glider.be
 2022-07-19 15:56:48 -06:00
Geert Uytterhoeven b06d7b458a gpio: GPIO_SAMA5D2_PIOBU should depend on ARCH_AT91 
The SAMA5D2 PIOBU is only present on some AT91/Microchip SoCs.  Hence
add a dependency on ARCH_AT91, to prevent asking the user about this
driver when configuring a kernel without AT91/Microchip SoC support.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
 2022-07-19 09:57:41 +02:00
Geert Uytterhoeven 31212be403 dt-bindings: gpio: renesas,rcar-gpio: R-Car V3U is R-Car Gen4 
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence move its compatible value to the R-Car Gen4 section.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
 2022-07-19 09:56:51 +02:00
Geert Uytterhoeven 806a449725 serial: 8250: SERIAL_8250_ASPEED_VUART should depend on ARCH_ASPEED 
The Aspeed Virtual UART is only present on Aspeed BMC platforms.  Hence
add a dependency on ARCH_ASPEED, to prevent asking the user about this
driver when configuring a kernel without Aspeed BMC support.

Reviewed-by: Jeremy Kerr <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/259138c372d433005b4871789ef9ee8d15320307.1657528861.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <[email protected]>
 2022-07-14 16:27:55 +02:00
Geert Uytterhoeven ce05f30dc3 Merge tag 'renesas-r9a07g043-dt-binding-defs-tag2' into HEAD 
Renesas RZ/Five DT Binding Definitions

Clock and reset definitions for the Renesas RZ/Five (R9A07G043) SoC,
shared by driver and DT source files.
 2022-07-05 09:20:22 +02:00
Geert Uytterhoeven 3896b8f092 arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order 
The scif0 nodes were accidentally inserted after the scif3 nodes,
breaking alphabetical sort order.

Fixes: 1614c8624a ("arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/2fe0e782351c202ed009dcd658f4bceec8f3a56d.1656951240.git.geert+renesas@glider.be
 2022-07-05 09:10:18 +02:00
Geert Uytterhoeven d684e0a52d sh: convert nommu io{re,un}map() to static inline functions 
Recently, nommu iounmap() was converted from a static inline function to a
macro again, basically reverting commit 4580ba4ad2 ("sh: Convert
iounmap() macros to inline functions").  With -Werror, this leads to build
failures like:

    drivers/iio/adc/xilinx-ams.c: In function `ams_iounmap_ps':
    drivers/iio/adc/xilinx-ams.c:1195:14: error: unused variable `ams' [-Werror=unused-variable]
     1195 |  struct ams *ams = data;
	  |              ^~~

Fix this by replacing the macros for ioremap() and iounmap() by static
inline functions, based on <asm-generic/io.h>.

Link: https://lkml.kernel.org/r/8d1b1766260961799b04035e7bc39a7f59729f72.1655708312.git.geert+renesas@glider.be
Fixes: 13f1fc870d ("sh: move the ioremap implementation out of line")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reported-by: kernel test robot <[email protected]>
Reported-by: Jonathan Cameron <[email protected]>
Acked-by: Jonathan Cameron <[email protected]>
Reviewed-by: Christoph Hellwig <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
 2022-07-03 15:42:32 -07:00
Geert Uytterhoeven 5cd561688b drm/bridge: imx: i.MX8 bridge drivers should depend on ARCH_MXC 
The various Freescale i.MX8 display bridges are only present on
Freescale i.MX8 SoCs.  Hence add a dependency on ARCH_MXC, to prevent
asking the user about these drivers when configuring a kernel without
i.MX SoC support.

Fixes: e60c435484 ("drm/bridge: imx: Add LDB support for i.MX8qm")
Fixes: 3818715f62 ("drm/bridge: imx: Add LDB support for i.MX8qxp")
Fixes: 96988a526c ("drm/bridge: imx: Add i.MX8qxp pixel link to DPI support")
Fixes: 1ec17c26bc ("drm/bridge: imx: Add i.MX8qm/qxp display pixel link support")
Fixes: 93e163a9e0 ("drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Liu Ying <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/42c542b53a1c8027b23a045045fbb7b34479913d.1656072500.git.geert+renesas@glider.be
 2022-07-01 10:26:38 +02:00
Geert Uytterhoeven 2f805cba10 pinctrl: renesas: r8a779f0: Remove unused POC2 
The POWER Condition Control Register 2 (POC2) is unused, and the
documentation does not define any valid bits.  Remove it.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/d8a9ea39b49d24e39f4da3f00b64bce34016887d.1655301529.git.geert+renesas@glider.be
 2022-06-29 15:53:04 +02:00
Geert Uytterhoeven a71a62dd5e dt-bindings: pinctrl: renesas: Remove spaces before #define 
Remove spaces at the beginning of lines with #defines.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/5188ef93a911ce3781b16530fdebbf0f0af462b6.1655301264.git.geert+renesas@glider.be
 2022-06-29 15:21:58 +02:00
Geert Uytterhoeven 8267839530 ARM: dts: renesas: Fix DA9063 watchdog subnode names 
make dtbs_check:

    arch/arm/boot/dts/r8a7791-koelsch-single-memory-node.dtb: pmic@58: 'wdt' does not match any of the regexes: 'pinctrl-[0-9]+'
	    From schema: Documentation/devicetree/bindings/mfd/dlg,da9063.yaml
    ...

Change the watchdog child node names to match the DA9063 DT bindings and
the Generic Names Recommendation in the Devicetree Specification.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/1dafdce285f7d14bec9e2033ac87fb30135895db.1655818230.git.geert+renesas@glider.be
 2022-06-29 15:17:46 +02:00
Geert Uytterhoeven f48cb21a28 arm64: dts: renesas: r8a779m8: Drop operating points above 1.5 GHz 
The highest-performance mode for the Cortex-A57 CPU cores supported on
R-Car H3Ne (R8A779M8) is the Power Optimized (1.5 GHz) mode.  The Normal
(1.6 GHz) and High Performance (1.7 GHz) modes are not supported.

Hence drop the "turbo-mode" entries from the operating points table
inherited from r8a77951.dtsi.

Fixes: 6e87525d75 ("arm64: dts: renesas: Add Renesas R8A779M8 SoC support")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/aeb4530f7fbac8329b334dcb169382c836a5f32d.1655458564.git.geert+renesas@glider.be
 2022-06-29 15:16:06 +02:00
Geert Uytterhoeven 0553b288ab MAINTAINERS: Add Renesas SoC DT bindings to Renesas Architecture sections 
While Renesas SoC DT bindings documents started to appear under
Documentation/devicetree/bindings/soc/renesas, these are not yet covered
by the file and directory patterns in the Renesas ARM/ARM64 Architecture
sections.

Add the missing patterns.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/f99c03a95a103517418f0b23d3da45e0dd0ffb3b.1655456310.git.geert+renesas@glider.be
 2022-06-29 15:14:32 +02:00
Geert Uytterhoeven 19e506b317 eeprom: at25: Rework buggy read splitting 
The recent change to split reads into chunks has several problems:
  1. If an SPI controller has no transfer size limit, max_chunk is
     SIZE_MAX, and num_msgs becomes zero, causing no data to be read
     into the buffer, and exposing the original contents of the buffer
     to userspace,
  2. If the requested read size is not a multiple of the maximum
     transfer size, the last transfer reads too much data, overflowing
     the buffer,
  3. The loop logic differs from the write case.

Fix the above by:
  1. Keeping track of the number of bytes that are still to be
     transferred, instead of precalculating the number of messages and
     keeping track of the number of bytes tranfered,
  2. Calculating the transfer size of each individual message, taking
     into account the number of bytes left,
  3. Switching from a "while"-loop to a "do-while"-loop, and renaming
     "msg_count" to "segment".

While at it, drop the superfluous cast from "unsigned int" to "unsigned
int", also from at25_ee_write(), where it was probably copied from.

Fixes: 0a35780c75 ("eeprom: at25: Split reads into chunks and cap write size")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/7ae260778d2c08986348ea48ce02ef148100e088.1655817534.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <[email protected]>
 2022-06-27 16:21:05 +02:00
Geert Uytterhoeven c223a38d62 mtd: hyperbus: rpc-if: Fix RPM imbalance in probe error path 
If rpcif_hw_init() fails, Runtime PM is left enabled.

Fixes: b04cc0d912 ("memory: renesas-rpc-if: Add support for RZ/G2L")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Reviewed-by: Sergey Shtylyov <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/f3070e1af480cb252ae183d479a593dbbf947685.1655457790.git.geert+renesas@glider.be
 2022-06-24 20:47:36 +02:00
Geert Uytterhoeven 9faa1c8f92 dt-bindings: usb: ehci: Increase the number of PHYs 
"make dtbs_check":

    arch/arm/boot/dts/r8a77470-iwg23s-sbc.dtb: usb@ee080100: phys: [[17, 0], [31]] is too long
	    From schema: Documentation/devicetree/bindings/usb/generic-ehci.yaml
    arch/arm/boot/dts/r8a77470-iwg23s-sbc.dtb: usb@ee0c0100: phys: [[17, 1], [33], [21, 0]] is too long
	    From schema: Documentation/devicetree/bindings/usb/generic-ehci.yaml

Some USB EHCI controllers (e.g. on the Renesas RZ/G1C SoC) have multiple
PHYs.  Increase the maximum number of PHYs to 3, which is sufficient for
now.

Fixes: 0499220d6d ("dt-bindings: Add missing array size constraints")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/c5d19e2f9714f43effd90208798fc1936098078f.1655301043.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <[email protected]>
 2022-06-21 16:26:54 +02:00
Geert Uytterhoeven 0f074c1c95 dt-bindings: usb: ohci: Increase the number of PHYs 
"make dtbs_check":

    arch/arm/boot/dts/r8a77470-iwg23s-sbc.dtb: usb@ee080000: phys: [[17, 0], [31]] is too long
	    From schema: Documentation/devicetree/bindings/usb/generic-ohci.yaml
    arch/arm/boot/dts/r8a77470-iwg23s-sbc.dtb: usb@ee0c0000: phys: [[17, 1], [33], [21, 0]] is too long
	    From schema: Documentation/devicetree/bindings/usb/generic-ohci.yaml

Some USB OHCI controllers (e.g. on the Renesas RZ/G1C SoC) have multiple
PHYs.  Increase the maximum number of PHYs to 3, which is sufficient for
now.

Fixes: 0499220d6d ("dt-bindings: Add missing array size constraints")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/0112f9c8881513cb33bf7b66bc743dd08b35a2f5.1655301203.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <[email protected]>
 2022-06-21 16:26:43 +02:00
Geert Uytterhoeven 3c7742a45c ARM: dts: rza2mevb: Fix LED node names 
"make dtbs_check":

    arch/arm/boot/dts/r7s9210-rza2mevb.dtb: leds: 'green', 'red' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
	    From schema: Documentation/devicetree/bindings/leds/leds-gpio.yaml

Fix this by prefixing the LED node names with "led-".

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Kieran Bingham <[email protected]>
Link: https://lore.kernel.org/r/f6e2883c16803b5d90a26c38d8e61ad15096089c.1655301593.git.geert+renesas@glider.be
 2022-06-17 09:46:20 +02:00
Geert Uytterhoeven 62e8a53431 arm64: dts: renesas: Fix thermal-sensors on single-zone sensors 
"make dtbs_check":

    arch/arm64/boot/dts/renesas/r8a774c0-cat874.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[74], [0]] is too long
    arch/arm64/boot/dts/renesas/r8a774c0-ek874.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[79], [0]] is too long
    arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[82], [0]] is too long
    arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[87], [0]] is too long
    arch/arm64/boot/dts/renesas/r8a77990-ebisu.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[105], [0]] is too long
	    From schema: Documentation/devicetree/bindings/thermal/thermal-zones.yaml

Indeed, the thermal sensors on R-Car E3 and RZ/G2E support only a single
zone, hence #thermal-sensor-cells = <0>.

Fix this by dropping the bogus zero cell from the thermal sensor
specifiers.

Fixes: 8fa7d18f9e ("arm64: dts: renesas: r8a77990: Create thermal zone to support IPA")
Fixes: 8438bfda9d ("arm64: dts: renesas: r8a774c0: Create thermal zone to support IPA")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Niklas Söderlund <[email protected]>
Link: https://lore.kernel.org/r/28b812fdd1fc3698311fac984ab8b91d3d655c1c.1655301684.git.geert+renesas@glider.be
 2022-06-17 09:46:20 +02:00
Geert Uytterhoeven e5fba0bc82 arm64: dts: renesas: r8a779f0: Add CPU core clocks 
Describe the clocks for the eight Cortex-A55 CPU cores.
CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ.
CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ.

For now no operating points are defined.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Yoshihiro Shimoda <[email protected]>
Tested-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/c502087f9affa86dd665def0d990d277a51cc75c.1654701480.git.geert+renesas@glider.be
 2022-06-17 09:46:19 +02:00
Geert Uytterhoeven 2dcb78d226 arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores 
Complete the description of the Cortex-A55 CPU cores and L3 cache
controllers on the Renesas R-Car S4-8 (R8A779F0) SoC, including CPU
topology and PSCI support for enabling CPU cores.

R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters.

Based on patches in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Yoshihiro Shimoda <[email protected]>
Tested-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/d6af5975090d5830cb053b52400439bd1cbe8fc7.1654701480.git.geert+renesas@glider.be
 2022-06-17 09:46:19 +02:00
Geert Uytterhoeven ffeca49a8b arm64: dts: renesas: r8a779f0: Add L3 cache controller 
Describe the cache configuration for the first Cortex-A55 CPU core on
the Renesas R-Car S4-8 (R8A779F0) SoC.

Extracted from a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Yoshihiro Shimoda <[email protected]>
Tested-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/a63715ce1d2d2fcc7ab987f7a1b40847965e8d6a.1654701480.git.geert+renesas@glider.be
 2022-06-17 09:46:19 +02:00
Geert Uytterhoeven 06279f82da arm64: dts: renesas: r8a779a0: Add CPU0 core clock 
Describe the clock for the first Cortex-A76 CPU core.
For now no operating points are defined.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/3ace4eea4ff1cdc0f7b8ea7d0433c1063d795785.1654701400.git.geert+renesas@glider.be
 2022-06-17 09:46:19 +02:00
Geert Uytterhoeven 650fd1d058 arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values 
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence update the compatible properties in various device nodes
to include family-specific compatible values for R-Car Gen4:
  - GPIO.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/b477eea0fc33a055d1b1874847e26614f68f5da0.1654701299.git.geert+renesas@glider.be
 2022-06-17 09:46:19 +02:00
Geert Uytterhoeven 774fecc7ec dt-bindings: soc: renesas: Move renesas,prr from arm to soc 
The Renesas Product Register DT binding is not a top-level DT binding,
hence it does not belong under Documentation/devicetree/bindings/arm/.
Move it to Documentation/devicetree/bindings/soc/renesas/.

While at it, change the license from GPL-2.0 (only) to GPL-2.0-only OR
BSD-2-Clause, to match common practices.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Simon Horman <[email protected]>
Link: https://lore.kernel.org/r/5f124fc332b4b866f5238ada7ac000f4639c88c3.1651495078.git.geert+renesas@glider.be
 2022-06-17 09:18:33 +02:00
Geert Uytterhoeven d5c10876c7 clk: renesas: r8a779f0: Add Z0 and Z1 clock support 
Add support for the Z0 and Z1 (Cortex-A55 Sub-System 0 (CPU 0-3) and
Sub-System 1 (CPU 4-7)) clocks on R-Car S4-8, based on the existing
support for Z clocks on R-Car Gen4.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/43009e25be1223a717e00c392cb2d416f5d47032.1654695893.git.geert+renesas@glider.be
 2022-06-17 09:11:36 +02:00
Geert Uytterhoeven 5cda442dc0 dt-bindings: phy: renesas: usb3-phy: Spelling s/funcional/functional/ 
Fix a misspelling of the word "functional".

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/3da9bd360e1c83007af0e0e90fa4e6c2b50fdab3.1652100633.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <[email protected]>
 2022-06-16 17:21:09 -07:00
Geert Uytterhoeven fc9e01676c dt-bindings: clock: renesas,rzg2l: Simplify header file references 
The bindings already uses <dt-bindings/clock/r9a0*-cpg.h> to refer to
the header files with DT binding definitions for core clocks.
Use more wildcards to simplify more references to these files.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/f274ad16010798dd4a45d2dca5f870da8acbb470.1654696009.git.geert+renesas@glider.be
 2022-06-13 11:53:18 +02:00
Geert Uytterhoeven 980bcaf339 clk: renesas: rza1: Remove struct rz_cpg 
The register block base pointer as stored in the reg member of the
rz_cpg structure is only used during initialization.  Hence move
it to a local variable, and pass it as a parameter to
rz_cpg_register_clock().

After this, the data member is the only remaining member of the rz_cpg
structure, so the whole structure can be replaced by the data member.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/2380285576edaa4ad3dc5eca7e0ca418f068c6ef.1654694831.git.geert+renesas@glider.be
 2022-06-13 11:53:18 +02:00
Geert Uytterhoeven 4448779839 clk: renesas: r8a7779: Remove struct r8a7779_cpg 
All but the data member of the r8a7779_cpg structure are unused, so the
whole structure can be replaced by the single member used.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/eb94c0f6c54a4f3a7e0e07f12781333a700c0a05.1654694831.git.geert+renesas@glider.be
 2022-06-13 11:53:18 +02:00
Geert Uytterhoeven 1cfeec2427 clk: renesas: r8a7778: Remove struct r8a7778_cpg 
All but the data member of the r8a7778_cpg structure are unused, so the
whole structure can be replaced by the single member used.

Remove the mapping of the CPG registers, as no code uses the mapped
registers.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/4123c1c40a901195f00a825d434553d2052829aa.1654694831.git.geert+renesas@glider.be
 2022-06-13 11:53:18 +02:00
Geert Uytterhoeven 3849716ad3 clk: renesas: sh73a0: Remove sh73a0_cpg.reg 
The register block base pointer as stored in the reg member of the
sh73a0_cpg structure is only used during initialization.  Hence move
it to a local variable, and pass it as a parameter to
sh73a0_cpg_register_clock().

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/5423e43d0cf518691965412fb510097d23ac5955.1654694831.git.geert+renesas@glider.be
 2022-06-13 11:53:18 +02:00
Geert Uytterhoeven a00d077aaa clk: renesas: r8a7740: Remove r8a7740_cpg.reg 
The register block base pointer as stored in the reg member of the
r8a7740_cpg structure is only used during initialization.  Hence move
it to a local variable, and pass it as a parameter to
r8a7740_cpg_register_clock().

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/7ec676bcc36ef1eda02c2db328c527fc5fd44e99.1654694831.git.geert+renesas@glider.be
 2022-06-13 11:53:18 +02:00
Geert Uytterhoeven 65d012e415 clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg 
The register block base pointer as stored in the reg member of the
r8a73a4_cpg structure is only used during initialization.  Hence move
it to a local variable, and pass it as a parameter to
r8a73a4_cpg_register_clock().

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/f835f3dfcf3bf754065e5002663952cc6341caac.1654694831.git.geert+renesas@glider.be
 2022-06-13 11:53:18 +02:00
Geert Uytterhoeven 4f5bc54d28 soc: renesas: rcar-sysc: Optimize rcar_sysc_area struct sizes 
Reduce the sizes of the rcar_sysc_area and rcar_gen4_sysc_area
structures:
  - parent is in the range [-1..32] or [-1..64], so s8 is sufficient,
  - flags needs just 3 bits (for now), so u8 is plenty.

This reduces kernel size by:
  - 288 bytes for an R-Car Gen1+Gen2 kernel (arm32),
  - 1772 bytes for an R-Car Gen3+Gen4 kernel (arm64).

Signed-off-by: Geert Uytterhoeven <[email protected]>
Tested-by: Wolfram Sang <[email protected]>
Reviewed-by: Yoshihiro Shimoda <[email protected]>
Tested-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/cbbc8f464743d636895c048de61aa610d75392de.1654701156.git.geert+renesas@glider.be
 2022-06-13 11:43:50 +02:00
Geert Uytterhoeven bccceabb92 soc: renesas: r8a779a0-sysc: Fix A2DP1 and A2CV[2357] PDR values 
The PDR values for the A2DP1 and A2CV[2357] power areas on R-Car V3U are
incorrect (copied-and-pasted from A2DP0 and A2CV[0146]).
Fix them.

Reported-by: Renesas Vietnam via Yoshihiro Shimoda <[email protected]>
Fixes: 1b4298f000 ("soc: renesas: r8a779a0-sysc: Add r8a779a0 support")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/87bc2e70ba4082970cf8c65871beae4be3503189.1654696188.git.geert+renesas@glider.be
 2022-06-13 11:43:50 +02:00
Geert Uytterhoeven 7e1ab5a8a3 arm64: defconfig: Enable R8A779G0 SoC 
Enable the Renesas R-Car V4H (R8A779G0) SoC in the ARM64 defconfig.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/eb672fad7c9a340812079a07539d670f42f4ad41.1654855105.git.geert+renesas@glider.be
 2022-06-13 11:02:47 +02:00
Geert Uytterhoeven 36e2da1125 ARM: shmobile: defconfig: Refresh for v5.19-rc1 
Refresh the defconfig for Renesas ARM systems:
  - Move CONFIG_SLAB=y (moved in commit 7b42f1041c ("mm: Kconfig:
    move swap and slab config options to the MM section")),
  - Enable CONFIG_RENESAS_RZN1WDT (RZN1D-DB),
  - Enable CONFIG_RTC_DRV_RZN1 (RZN1-DB).

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/7ef31a41e1a15d0cedeb6cfc496ce70a78102e32.1654855000.git.geert+renesas@glider.be
 2022-06-13 11:02:46 +02:00
Geert Uytterhoeven e8ecf73adb dmaengine: dmatest: Replace symbolic permissions by octal permissions 
Octal permissions are easier to read.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/a745b883288f95e999b71fac677bbc2daa13c22d.1654702928.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <[email protected]>
 2022-06-09 11:31:57 +05:30
Geert Uytterhoeven 5f89b97e1f dmaengine: dmatest: Remove spaces before tabs 
Scripts/checkpath.pl says "please, no space before tabs".

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/d863916120d043e3f9dd2f2670238c34f68f7d5f.1654702886.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <[email protected]>
 2022-06-09 11:31:57 +05:30
Geert Uytterhoeven 514c62048b fbcon: Remove obsolete reference to initmem_freed 
initmem_freed was removed in v2.1.124, and the underlying issue was
fixed for good in commit 92b004d1aa ("video/logo: prevent use of
logos after they have been freed").

Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/b8b9147a48e233fe32e072f2085c7b413cd92a00.1654702835.git.geert+renesas@glider.be
 2022-06-08 18:29:45 +02:00
Geert Uytterhoeven f06e4c9ec8 dt-bindings: display: bridge: sil,sii9022: Convert to json-schema 
Convert the Silicon Image sii902x HDMI bridge Device Tree binding
documentation to json-schema.

Add missing sil,sii9022-cpi and sil,sii9022-tpi compatible values.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/2f8e12b4980a82788c1dd413ceedf8d144fdca91.1652967387.git.geert+renesas@glider.be
 2022-06-06 14:22:37 -05:00
Geert Uytterhoeven 67c7fc6cd9 memory: omap-gpmc: OMAP_GPMC should depend on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 
The Texas Instruments OMAP General Purpose Memory Controller (GPMC) is
only present on TI OMAP2/3/4/5, Keystone, AM33xx, AM43x, DRA7xx, TI81xx,
and K3 SoCs.  Hence add a dependency on ARCH_OMAP2PLUS || ARCH_KEYSTONE
|| ARCH_K3, to prevent asking the user about this driver when
configuring a kernel without OMAP2+, Keystone, or K3 SoC family support.

Fixes: be34f45f0d ("memory: omap-gpmc: Make OMAP_GPMC config visible and selectable")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/f6780f572f882ed6ab5934321942cf2b412bf8d1.1652174849.git.geert+renesas@glider.be
Signed-off-by: Krzysztof Kozlowski <[email protected]>
 2022-06-06 11:10:53 +02:00
Geert Uytterhoeven 5cf12ac949 arm64: dts: renesas: Rename numbered regulators 
Numbered regulators are prone to conflicts, causing silent overwrites
(see e.g. [1]).

Make conflicts less likely to happen by renaming all numbered regulators
to names reflecting the regulator's purposes.

[1] commit 45f5d5a9e3 ("arm64: dts: renesas: r8a77995: draak: Fix
    backlight regulator name").

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/b90dfeb834c4d7dabd22bf03396f33df58f54507.1652264651.git.geert+renesas@glider.be
 2022-06-06 10:29:04 +02:00
Geert Uytterhoeven 7512af9f78 arm64: dts: renesas: beacon: Fix regulator node names 
Currently there are two nodes named "regulator_camera".  This causes the
former to be overwritten by the latter.

Fix this by renaming them to unique names, using the preferred hyphen
instead of an underscore.

While at it, update the name of the audio regulator (which was added in
the same commit) to use a hyphen.

Fixes: a1d8a344f1 ("arm64: dts: renesas: Introduce r8a774a1-beacon-rzg2m-kit")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/a9ac82bdf108162487289d091c53a9b3de393f13.1652263918.git.geert+renesas@glider.be
 2022-06-06 10:29:04 +02:00
Geert Uytterhoeven 6c465408a7 dt-bindings: net: adin: Fix adi,phy-output-clock description syntax 
"make dt_binding_check":

    Documentation/devicetree/bindings/net/adi,adin.yaml:40:77: [error] syntax error: mapping values are not allowed here (syntax)

The first line of the description ends with a colon, hence the block
needs to be marked with a "|".

Fixes: 1f77204e11 ("dt-bindings: net: adin: document phy clock output properties")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/6fcef2665a6cd86a021509a84c5956ec2efd93ed.1653401420.git.geert+renesas@glider.be
Signed-off-by: Jakub Kicinski <[email protected]>
 2022-05-25 22:03:45 -07:00
Geert Uytterhoeven 5a7cb9f397 gpio: sifive: Make the irqchip immutable 
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.  Following this change the following warning is
now observed for the sifive driver:

    gpio gpiochip1: (38001000.gpio-controller): not an immutable chip, please consider fixing it!

Fix this by making the irqchip in the sifive driver immutable.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Reviewed-by: Damien Le Moal <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
 2022-05-24 16:35:52 +02:00
Geert Uytterhoeven 718b972d32 gpio: rcar: Make the irqchip immutable 
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.  Following this change the following warning is
now observed for the gpio-rcar driver:

    gpio gpiochip0: (e6050000.gpio): not an immutable chip, please consider fixing it!

Fix this by making the irqchip in the gpio-rcar driver immutable.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
 2022-05-24 16:35:49 +02:00
Geert Uytterhoeven 61550be779 gpio: pcf857x: Make the irqchip immutable 
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.  Following this change the following warning is
now observed for the pcf857x driver:

    gpio gpiochip1: (pcf8575): not an immutable chip, please consider fixing it!

Fix this by making the irqchip in the pcf857x driver immutable.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
 2022-05-24 16:35:42 +02:00
Geert Uytterhoeven ac2f6f9385 gpio: pca953x: Make the irqchip immutable 
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.  Following this change the following warning is
now observed for the pca953x driver:

    gpio gpiochip7: (0-0020): not an immutable chip, please consider fixing it!

Fix this by making the irqchip in the pca953x driver immutable.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
 2022-05-24 16:35:37 +02:00
Geert Uytterhoeven cfc2b00ebe gpio: dwapb: Make the irqchip immutable 
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.  Following this change the following warning is
now observed for the dwapb driver:

    gpio gpiochip0: (50200000.gpio): not an immutable chip, please consider fixing it!

Fix this by making the irqchip in the dwapb driver immutable.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Damien Le Moal <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
 2022-05-24 16:35:26 +02:00
Geert Uytterhoeven 9215a90dd5 dt-bindings: watchdog: renesas,wdt: R-Car V3U is R-Car Gen4 
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence move its compatible value to the R-Car Gen4 section.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Link: https://lore.kernel.org/r/2882a6de3905a57ae62d91060d27521af43c4068.1651497024.git.geert+renesas@glider.be
Signed-off-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
 2022-05-21 10:09:31 +02:00
Geert Uytterhoeven 644291ebec dt-bindings: input: touchscreen: ilitek_ts_i2c: Absorb ili2xxx bindings 
While Linux uses a different driver, the Ilitek
ILI210x/ILI2117/ILI2120/ILI251x touchscreen controller Device Tree
binding documentation is very similar.

  - Drop the fixed reg value, as some controllers use a different
    address,
  - Make reset-gpios optional, as it is not always wired.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/0c5f06c9d262c1720b40d068b6eefe58ca406601.1638539806.git.geert+renesas@glider.be
 2022-05-19 15:54:06 -05:00
Geert Uytterhoeven 48bd5c381c pinctrl: starfive: Make the irqchip immutable 
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.  Following this change the following warning is
now observed for the starfive driver:

    gpio gpiochip0: (11910000.pinctrl): not an immutable chip, please consider fixing it!

Fix this by making the irqchip in the starfive driver immutable.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/5eb66be34356afd5eb0ea9027329e0939d03d3a0.1652884852.git.geert+renesas@glider.be
Signed-off-by: Linus Walleij <[email protected]>
 2022-05-19 15:16:29 +02:00
Geert Uytterhoeven 8e1f78a921 arm64/sve: Move sve_free() into SVE code section 
If CONFIG_ARM64_SVE is not set:

    arch/arm64/kernel/fpsimd.c:294:13: warning: ‘sve_free’ defined but not used [-Wunused-function]

Fix this by moving sve_free() and __sve_free() into the existing section
protected by "#ifdef CONFIG_ARM64_SVE", now the last user outside that
section has been removed.

Fixes: a1259dd807 ("arm64/sve: Delay freeing memory in fpsimd_flush_thread()")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/cd633284683c24cb9469f8ff429915aedf67f868.1652798894.git.geert+renesas@glider.be
Signed-off-by: Catalin Marinas <[email protected]>
 2022-05-18 14:44:36 +01:00
Geert Uytterhoeven a3641ca416 net: smc911x: Fix min() use in debug code 
If ENABLE_SMC_DEBUG_PKTS=1:

    drivers/net/ethernet/smsc/smc911x.c: In function ‘smc911x_hardware_send_pkt’:
    include/linux/minmax.h:20:28: error: comparison of distinct pointer types lacks a cast [-Werror]
       20 |  (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
	  |                            ^~
    drivers/net/ethernet/smsc/smc911x.c:483:17: note: in expansion of macro ‘min’
      483 |  PRINT_PKT(buf, min(len, 64));

Fix this by making the constant unsigned, to match the type of "len".
While at it, replace the other missed ternary operator by min(), too.

Convert the dummy PRINT_PKT() from a macro to a static inline function,
to catch mistakes like this without having to enable debug options
manually.

Fixes: 5ff0348b7f ("net: smc911x: replace ternary operator with min()")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
 2022-05-18 14:13:09 +01:00
Geert Uytterhoeven 48b171dbf7 dt-bindings: can: renesas,rcar-canfd: Make interrupt-names required 
The Renesas R-Car CAN FD Controller always uses two or more interrupts.
Make the interrupt-names properties a required property, to make it
easier to identify the individual interrupts.

Update the example accordingly.

Link: https://lore.kernel.org/all/a68e65955e0df4db60233d468f348203c2e7b940.1651512451.git.geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Marc Kleine-Budde <[email protected]>
 2022-05-16 22:07:38 +02:00
Geert Uytterhoeven 94737ef56b can: ctucanfd: Let users select instead of depend on CAN_CTUCANFD 
The CTU CAN-FD IP core is only useful when used with one of the
corresponding PCI/PCIe or platform (FPGA, SoC) drivers, which depend on
PCI resp. OF.

Hence make the users select the core driver code, instead of letting
then depend on it.  Keep the core code config option visible when
compile-testing, to maintain compile-coverage.

Link: https://lore.kernel.org/all/887b7440446b6244a20a503cc6e8dc9258846706.1652104941.git.geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Pavel Pisa <[email protected]>
Signed-off-by: Marc Kleine-Budde <[email protected]>
 2022-05-16 22:03:45 +02:00
Geert Uytterhoeven a9ad582236 drm: bridge: DRM_FSL_LDB should depend on ARCH_MXC 
The Freescale i.MX8MP LDB bridge is only present on Freescale i.MX8MP
SoCs.  Hence add a dependency on ARCH_MXC, to prevent asking the user
about this driver when configuring a kernel without i.MX SoC support.

Fixes: 463db5c2ed ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Robert Foss <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/449e08ca791a3ca308de5477c1bdc1f6eb1b34e7.1652104211.git.geert+renesas@glider.be
 2022-05-16 16:56:12 +02:00
Geert Uytterhoeven b965182aee dt-bindings: renesas,rcar-dmac: R-Car V3U is R-Car Gen4 
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence move its compatible value to the R-Car Gen4 section.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/e6e4cf701f3a43b061b9c3f7f0adc4d6addd4722.1651497024.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <[email protected]>
 2022-05-16 17:00:55 +05:30
Geert Uytterhoeven 66d7a40beb mtd: nand: MTD_NAND_ECC_MEDIATEK should depend on ARCH_MEDIATEK 
The MediaTek Hardware ECC Engine is only present on MediaTek MT27xx and
MT76xx SoCs.  The driver for this engine is a dependency for the
MediaTek NAND controller (MTD_NAND_MTK) and the MediaTek SPI NAND Flash
Interface (SPI_MTK_SNFI) drivers, both of which already depend on
ARCH_MEDIATEK.

Hence add a dependency on ARCH_MEDIATEK to the Hardware ECC Engine
driver, too, to prevent asking the user about this driver when
configuring a kernel without MediaTek SoC support.

Fixes: 4fd62f15af ("mtd: nand: make mtk_ecc.c a separated module")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/bb9568e825d4bc7506870b03836baa91bcc4b725.1652104136.git.geert+renesas@glider.be
 2022-05-12 16:43:04 +02:00
Geert Uytterhoeven d7f49cb451 Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-arm-dt-for-v5.19 
Renesas RZ/V2M DT Binding Definitions

Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by
driver and DT source files.
 2022-05-06 11:09:45 +02:00
Geert Uytterhoeven a1721bbbdb arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values 
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence update the compatible properties in various device nodes
to include family-specific compatible values for R-Car Gen4 instead of
R-Car Gen3:
  - DMAC,
  - (H)SCIF,
  - I2C,
  - IPMMU,
  - WDT.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/73cea9d5e1a6639422c67e4df4285042e31c9fd5.1651497071.git.geert+renesas@glider.be
 2022-05-06 11:09:34 +02:00
Geert Uytterhoeven 6af663af3c arm64: dts: renesas: Add interrupt-names to CANFD nodes 
The Renesas R-Car CAN-FD Controller on R-Car Gen3 and RZ/G2 SoCs has two
interrupts.  Add interrupt-names properties to all CAN-FD device nodes
to identify the individual interrupts, so we can make this property a
required property in the DT bindings.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/10eef1e20372af4a156b06df8e5124666ec7c6b6.1651512451.git.geert+renesas@glider.be
 2022-05-06 11:09:34 +02:00
Geert Uytterhoeven 9ae081f470 serial: 8250: pxa: Remove unneeded <linux/pm_runtime.h> 
The 8250 PXA driver never used Runtime PM, so there was never a need to
include <linux/pm_runtime.h>.

Fixes: ab28f51c77 ("serial: rewrite pxa2xx-uart to use 8250_core")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/9fd96fba9bbbbdeb16af0dc07ae9dee21c8e297c.1651494971.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <[email protected]>
 2022-05-05 22:34:27 +02:00
Geert Uytterhoeven 174f86b879 serial: 8250: core: Remove unneeded <linux/pm_runtime.h> 
The last calls into Runtime PM were moved to 8250_port.c a long time
ago.

Fixes: b6830f6df8 ("serial: 8250: Split base port operations from universal driver")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/2545eaa7fc552013a5d04c4df027255204e64834.1651494971.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <[email protected]>
 2022-05-05 22:34:25 +02:00
Geert Uytterhoeven f26c65dacf dt-bindings: serial: renesas,scif: R-Car V3U is R-Car Gen4 
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence move its compatible value to the R-Car Gen4 section.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/c57ed00e85778380776330be6183c6861d843c22.1651497024.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <[email protected]>
 2022-05-05 22:33:16 +02:00
Geert Uytterhoeven e4de48da57 dt-bindings: serial: renesas,hscif: R-Car V3U is R-Car Gen4 
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence move its compatible value to the R-Car Gen4 section.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/dd734aaa4e5e0b32864b038b79eafe72907fb99f.1651497024.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <[email protected]>
 2022-05-05 22:33:13 +02:00
Geert Uytterhoeven 7bc53f59fb ARM: shmobile: rcar-gen2: Drop comma after OF match table sentinel 
It does not make sense to have a comma after a sentinel, as any new
elements must be added before the sentinel.

Add a comment to clarify the purpose of the empty element.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/baaa4df6284401eb126573eb1c8ea5a88705cc37.1646311858.git.geert+renesas@glider.be
 2022-05-05 12:32:40 +02:00
Geert Uytterhoeven 3238f82df0 ARM: shmobile: Drop commas after dt_compat sentinels 
It does not make sense to have a comma after a sentinel, as any new
elements must be added before the sentinel.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/ab4acc22eebb96a0747eb301c878b24b1200736a.1646311825.git.geert+renesas@glider.be
 2022-05-05 12:32:40 +02:00
Geert Uytterhoeven 27e7657a7c soc: renesas: R-Car V3U is R-Car Gen4 
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence reflect this in the SoC Family field.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/2bbecad7b6c24c0d5c1797b3f7f0733d5ba33842.1651497066.git.geert+renesas@glider.be
 2022-05-05 12:31:22 +02:00
Geert Uytterhoeven 049bddcb89 Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-clk-for-v5.19 
Renesas RZ/V2M DT Binding Definitions

Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by
driver and DT source files.
 2022-05-05 12:10:49 +02:00
Geert Uytterhoeven 53c58c08b4 clk: renesas: r9a07g044: Fix OSTM1 module clock name 
Fix a typo in the name of the "ostm1_pclk" clock.
This change has no run-time impact.

Fixes: 161450134a ("clk: renesas: r9a07g044: Add OSTM clock and reset entries")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be
 2022-05-05 12:10:21 +02:00
Geert Uytterhoeven fc883ed5a4 pinctrl: renesas: checker: Add reserved field checks 
Add checks for discovering registers with reserved fields that could
benefit from being described using variable-width reserved field
shorthands, reducing kernel size.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/f5a5159ba7b396e6f09dd3f23c864a74ed8e342d.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven 753278b4cb pinctrl: renesas: sh7786: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 79 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/22487451ff7d8cce0182354c9553f3b171cc34d9.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven 63a32f8286 pinctrl: renesas: sh7785: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 150 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/07a238f13f80674d86719a5e869c65a2e0b8c1c1.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven 2439a0dde4 pinctrl: renesas: sh7757: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 115 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/05c69ca8710134bb96ec8f7d18bafe42418f3510.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven 3a0a3c1be8 pinctrl: renesas: sh7734: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 161 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/18e476c0a9f0af5b5d511d1c4922c6e299d1847a.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven 2a1b67b565 pinctrl: renesas: sh7724: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 8 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/696dcad42a8b8395276301eb5dd5c5a895826f35.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven 98edc79d9a pinctrl: renesas: sh7723: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 105 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/5d7ef2fa02c2137d2d243fc183d18220c9aaf7b8.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven 72db29175f pinctrl: renesas: sh7722: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 396 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/c3965b6f9ea603b185924136f859c6eca7d5d6f4.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven aa9c0a767f pinctrl: renesas: sh7720: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 128 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/4b290f93a7edb1f91c97da90e67b7f6f3df62951.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven 064aa9aabe pinctrl: renesas: sh73a0: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 154 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/e74738b403cc15b3407e7568d323fdae8e7b30dd.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven d567210e4b pinctrl: renesas: sh7269: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 406 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/feb1e865c2b6abbc0db24243143ea09ad143f6df.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven 78fc20c155 pinctrl: renesas: sh7264: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 572 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/434c274f626b2eab3539fe2ab80c6eda164e07fa.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:28 +02:00
Geert Uytterhoeven 256c14196f pinctrl: renesas: sh7203: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 281 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/c625b4eee298b88c2ee47ed80b0dea5d02ed56d1.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven 170285f4c5 pinctrl: renesas: r8a779f0: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 183 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/e50f9c8ef1261b7ceb6b1be637d4019fe7312250.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven b9f01b20cc pinctrl: renesas: r8a779a0: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 556 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/7db3751ecf96fcc469bd14eeb02d69e565956151.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven ec255e1c15 pinctrl: renesas: r8a77995: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 422 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/d74af80fdb7b6d78b10634238a88e55a139e5c22.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven be525de9e8 pinctrl: renesas: r8a77990: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 226 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/924ba4505e33180e078ca72a1db8db13c193cbea.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven 23dbafd819 pinctrl: renesas: r8a77980: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 198 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/0bf6b069a794b3c56c0c9311ac4b2ada577a9cb7.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven 37362c77de pinctrl: renesas: r8a77970: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 268 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/33dd9bc41df888f132e2e6921d2ff38225b68105.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven 34856c5029 pinctrl: renesas: r8a7796: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 496 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/81f3586749bb1117c5636e9a9663d25e77cbe158.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven efd5ee63e9 pinctrl: renesas: r8a77965: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 496 bytes.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/2aff2f4c1ed6d834370ce6dd9379c8c93bfc0a92.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00