[Why]
some DP_SEC register defs and masks are missing.
[How]
add the missing defs and masks.
Signed-off-by: Max Tseng <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Qingqing Zhuo <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
There is a warning that triggers when pstate takes too long.
Pstate can take up to ~200us on Linux without hanging but
it is currently set to 40us.
[How]
Change the timeout for the warning to be 180us on Linux.
Signed-off-by: Victor Lu <[email protected]>
Reviewed-by: Roman Li <[email protected]>
Acked-by: Qingqing Zhuo <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
skip load smu and sdma fw on sriov due to sos,
ta and asd fw have been skipped for SIENNA_CICHLID.
V2:
move asic check into smu11
Signed-off-by: Stanley.Yang <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
S0ix only makes sense on APUs since they are part of the platform, so
only when the ASIC is APU should set amdgpu_acpi_is_s0ix_supported flag
to deal with the related situation.
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Without doing the soft reset, register mmSDMA0_GFX_RB_WPTR's value could not be
reset to 0 when sdma block resumes. That would cause the ring buffer's read and
write pointers not equal and ring test fail. So add the soft reset step.
Signed-off-by: Xiaomeng Hou <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
These are supported by Sienna Cichlid and should be
taken into consideration during DS control.
Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
RLC is halted when system suspend/shutdown. However, due to DPM enabled, PMFW is
unaware of RLC being halted and will continue sending messages, which would
eventually cause an ACPI hang. Use the system_feature_control interface to
notify SMU the status of RLC (Normal/OFF) thus enable/disable DPM feature.
Signed-off-by: Xiaomeng Hou <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Reviewed-by: Lazar Lijo <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
It's only used when CONFIG_DRM_AMD_DC_DCN is set. Fixes and set but
not used warning.
Acked-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Used for determining 2ND_USB20PORT support from firmware_capability.
Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
That will help to determine whether 2ND_USB20_PORT workaround is
needed for Sienna Cichlid.
Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Correct pipe offset calculation in is_pipe_enabled function,
it should be done in queues.
Signed-off-by: Jiansong Chen <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
After refactor our amdgpu_dm_atomic_commit, this function only invoke
drm_atomic_helper_commit. For this reason, this commit drops
amdgpu_dm_atomic_commit and add drm_atomic_helper_commit directly in the
atomic_commit hook.
v2: squash in warning fix (Alex)
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
The text output should not be more than a page, so only print the first
32 page table entries.
If we need all of them we can still look into the binary trace.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Shashank Sharma <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs
was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation
and amdgpu_gem_object_funcs setting into single function called
from both code paths.
Fixes: d693def4fd ("drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver")
v2: Use use amdgpu_gem_object_create() directly
v3: fix warning
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Andrey Grodzovsky <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
* Shutdown hook for GPU (to ensure GPU is idle before iommu goes away)
* GPU cooling device support
* DSI 7nm and 10nm phy/pll updates
* Additional sm8150/sm8250 DPU support (merge_3d and DSPP color
processing)
* Various DP fixes
* A whole bunch of W=1 fixes from Lee Jones
* GEM locking re-work (no more trylock_recursive in shrinker!)
* LLCC (system cache) support
* Various other fixes/cleanups
Signed-off-by: Dave Airlie <[email protected]>
From: Rob Clark <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGt0G=H3_RbF_GAQv838z5uujSmFd+7fYhL6Yg=23LwZ=g@mail.gmail.com
If we need to keep the stolen vga memory, make sure it is
at least as big as the legacy vga size.
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Rather than in late_init to avoid race conditions between freeing the
buffers and the initial modeset.
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
When using old WORKLOAD_PPLIB setting in smu10.h, there is problem that
it can't be able to switch to mak gpu clk during compute workload.
It needs to update WORKLOAD_PPLIB setting to fix this issue.
Signed-off-by: Changfeng <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
This patch is to remove one unsupported smu function, this function
will set the smu feature mask to disable all smu features in exception.
Because vangogh doesn't support to set the smu feature mask
by driver software, so this function is invalid for vangogh.
Signed-off-by: Xiaojian Du <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
Scatter/gather is APU feature.
But in dm it is limited only to Renoir.
Now we need it for Vangogh.
[How]
Apply system context setup in dm_init to all APUs.
Signed-off-by: Roman Li <[email protected]>
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
Scatter/gather feature is supported on Vangogh.
[How]
Add GTT domain support for Vangogh to enable
display buffers in system memory.
Signed-off-by: Roman Li <[email protected]>
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Release dmabuf reference before returning from kfd_ioctl_import_dmabuf.
amdgpu_amdkfd_gpuvm_import_dmabuf takes a reference to the underlying
GEM BO and doesn't keep the reference to the dmabuf wrapper.
Signed-off-by: Felix Kuehling <[email protected]>
Reviewed-by: Kent Russell <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
each sdma instance fw_version and feature_version
should be set right value when asic type isn't
between SIENNA_CICHILD and CHIP_DIMGREY_CAVEFISH
Signed-off-by: Stanley.Yang <[email protected]>
Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
When HDCP is on, some display would introduce audio noise during
HDCP handling.
[How]
Mute before HDCP handling when disabling core link. Unmute after
HDCP when enabling core link.
Signed-off-by: Roy Chan <[email protected]>
Reviewed-by: Martin Leung <[email protected]>
Acked-by: Eryk Brol <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
Without additional HostVM Latency, Renoir takes 2us longer to exit
self-refresh. This causes underflow in certain cases.
[How]
Add table for Renoir with updated sr exit latencies for WM set A.
Signed-off-by: Sung Lee <[email protected]>
Reviewed-by: Yongqiang Sun <[email protected]>
Reviewed-by: Roman Li <[email protected]>
Acked-by: Eryk Brol <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
At very high pixel clock, bandwidth calculation exceeds 32 bit size
and overflow value. This causes the resulting selection of link rate
to be inaccurate.
[How]
Change order of operation and use fixed point to deal with integer
accuracy. Also address bug found when forcing link rate.
Signed-off-by: Chris Park <[email protected]>
Reviewed-by: Wenjing Liu <[email protected]>
Acked-by: Eryk Brol <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
With the addition of dc_lock acquire before dc_link_handle_hpd_rx_irq,
there will be a deadlock situation where commit state sends a request
for payload allocation on MST and wait for HPD to process DOWN_REP.
[How]
Move forward the MST message handling in handle_hpd_rx_irq so that
it will not rely on call to dc_link_handle_hpd_rx_irq.
Signed-off-by: Qingqing Zhuo <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Acked-by: Eryk Brol <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
Currently, the offset provided to dcn30_set_disp_pattern_generator is
not forwarded to OPP for display pattern generation, resulting in
misaligned patterns and test failures.
[How]
Use the provided offset.
Signed-off-by: Wesley Chalmers <[email protected]>
Reviewed-by: Samson Tam <[email protected]>
Acked-by: Eryk Brol <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
Change in DCN10 to use IMMEDIATE_UPDATE mode for AFMT is not
reflected in DCN30 as it uses VPG.
[How]
Use IMMEDIATE_UPDATE mode for DCN30 in VPG.
Signed-off-by: Judy Cai <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Eryk Brol <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Max Tseng