Currently sm501fb_crtsrc_store() won't allow the routing to be changed via
echos from userspace in to the sysfs file. The reason for this is that the
strnicmp() for both heads uses a sizeof() for the string length, which ends
up being strlen() + 1 (\0 in the normal case, but the echo gives a newline,
which is where the issue occurs), this then causes a mismatch and
subsequently bails with the -EINVAL.
In addition to this, the hardcoded lengths were then used for the store
length that was returned, which ended up being erroneous and resulting in a
write error. There's also no point in returning anything but the full
length since it will -EINVAL out on a mismatch well before then anyways.
sizeof("string") is great for making sure you have space in your buffer,
but rather less so for string comparisons :-)
Signed-off-by: Paul Mundt <[email protected]>
Acked-by: Ben Dooks <[email protected]>
Cc: "Antonino A. Daplas" <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
This tidies up some of the rts7751r2d mess and gets it booting
again. Update the defconfig, too.
Signed-off-by: Masayuki Hosokawa <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
Neither of these have had any maintenance in years, and there's
no interest in keeping them straggling along. These have already
been slated for removal some time, so finally just get rid of them.
Signed-off-by: Paul Mundt <[email protected]>
Tidy up the R7780RP I/O mapping routines and switch the
pata_platform resources to IORESOURCE_MEM types, killing off
the useless port->addr conversion.
This fixes up R7780RP to boot after the recent devres conversion.
Signed-off-by: Paul Mundt <[email protected]>
This ended up causing problems for older parts (particularly ones
using PTEA). Revert this for now, it can be added back in once it's
had some more testing.
Signed-off-by: Paul Mundt <[email protected]>
This consolidates the various board heartbeat LED implementations,
used for strobing the load average across a LED bank. Those boards
not implementing a full bank can hook in via the LED class.
We leave the compat hook in the machvec for now until those non-banked
boards are able to migrate to the drivers/leds.
Signed-off-by: Paul Mundt <[email protected]>
This is used by the libc for parsing CPU capability flags passed
via the ELF auxvt, needed for run-time selection of atomic opcodes
amongst other things.
Signed-off-by: Paul Mundt <[email protected]>
Convert some of the global flush users over to using the local variants
that don't need to use the global routines.
Signed-off-by: Paul Mundt <[email protected]>
Rename the existing flush routines to local_ variants for use by
the IPI-backed global flush routines on SMP.
Signed-off-by: Paul Mundt <[email protected]>
There are a lot of bogus cpu_data-> references that only end up working
for the boot CPU, convert these to current_cpu_data to fixup SMP.
Signed-off-by: Paul Mundt <[email protected]>
Previously this was implemented using a global cache, cache
this per-CPU instead and bump up the number of context IDs to
match NR_CPUS.
Signed-off-by: Paul Mundt <[email protected]>
Only SH-4 needs to set _PAGE_WT when using write-through caching,
don't attempt to set it on SH-3 where it ends up being a reserved
bit.
Signed-off-by: Paul Mundt <[email protected]>
This converts the lazy dcache handling to the model described in
Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks
used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a
bonus, this slightly cuts down on the cache flushing frequency.
With that and the PTEA handling out of the way, the update_mmu_cache()
implementations can be consolidated, and we no longer have to worry
about which configuration the cache is in for the SH7705 case.
And finally, explicitly disable the lazy writeback on SMP (SH-4A).
Signed-off-by: Paul Mundt <[email protected]>
There were a few more things that needed fixing up, namely THREAD_SIZE
and the TLB miss handler where certain PTRS_PER_PGD == PTRS_PER_PTE
assumptions were being made.
Signed-off-by: Paul Mundt <[email protected]>
The iVDR clock enable bit happens to actually reside in a rather
different place than what is documented, so fix it up accordingly.
This fixes up SATA boot for some of the R7780RP boards that didn't
default-enable the clock in the loader.
Signed-off-by: Paul Mundt <[email protected]>
-m2 doesn't end up working particularly well when we've got a constrained
toolchain target. Switch to the same semantics used by SH-4A to attempt
to get it right. Spotted by Alex Song <[email protected]>.
Signed-off-by: Paul Mundt <[email protected]>
This rips out most of the needlessly complicated sh_bios and kgdb
trap handling, and forces it all through a common fast dispatch path.
As more debug traps are inserted, it's important to keep them in sync
for all of the parts, not just SH-3/4.
As the SH-2 parts are unable to do traps in the >= 0x40 range, we
restrict the debug traps to the 0x30-0x3f range on all parts, and
also bump the kgdb breakpoint trap down in to this range (from 0xff
to 0x3c) so it's possible to use for nommu.
Optionally, this table can be padded out to catch spurious traps for
SH-3/4, but we don't do that yet..
Signed-off-by: Paul Mundt <[email protected]>
At the moment the inode/dentry cache hash tables (common by way of
alloc_large_system_hash()) are incorrectly sized by their respective
detection logic when we attempt to use large base pages on systems with
little memory.
This results in odd behaviour when using a 64kB PAGE_SIZE, such as:
Dentry cache hash table entries: 8192 (order: -1, 32768 bytes)
Inode-cache hash table entries: 4096 (order: -2, 16384 bytes)
The mount cache hash table is seemingly the only one that gets this right
by directly taking PAGE_SIZE in to account.
The following patch attempts to catch the bogus values and round it up to
at least 0-order.
Signed-off-by: Paul Mundt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
This was inadvertently broken when the entry.S code split up,
restore the missing branch and get subsequent traps working
under debug again. This manifested itself as a lockup when
attempting to reload the VBR base.
Signed-off-by: Paul Mundt <[email protected]>
SH-2 and SH-2A need to use a different syscall base for the trapa
vector than the other parts, so fixup the logic in the kernel_execve()
case.
Signed-off-by: Paul Mundt <[email protected]>
Some time ago the schedule frame size changed and we failed to reflect
this in get_wchan() at the time. This first popped up as a problem on
SH7751R where schedule_frame ended up being unaligned and generating
an unaligned trap. This fixes it up again..
Signed-off-by: Paul Mundt <[email protected]>
Previously we haven't been doing anything with verbose BUG() reporting,
and we've been relying on the oops path for handling BUG()'s, which is
rather sub-optimal.
This switches BUG handling to use a fixed trapa vector (#0x3e) where we
construct a small bug frame post trapa instruction to get the context
right. This also makes it trivial to wire up a DIE_BUG for the atomic
die chain, which we couldn't really do before.
Signed-off-by: Paul Mundt <[email protected]>
We have a few different ways to do the atomic operations, so split
them out in to different headers rather than bloating atomic.h.
Kernelspace gUSA will take this up to a third implementation.
Signed-off-by: Paul Mundt <[email protected]>
In the 64-bit PTE case there's no point in restricting the encoding
to the low bits of the PTE, we can instead bump all of this up to
the high 32 bits and extend PTE_FILE_MAX_BITS to 32, adopting the
same convention used by x86 PAE.
There's a minor discrepency between the number of bits used for the
swap type encoding between 32 and 64-bit PTEs, but this is unlikely
to cause any problem given the extended offset.
Signed-off-by: Paul Mundt <[email protected]>
This looks like a result of too many auto-merges. The
CONFIG_ARCH_VERSATILE case was handled a total of 6 times.
This kills 5 of them.
Signed-off-by: Paul Mundt <[email protected]>
--
drivers/net/smc91x.h | 90 ---------------------------------------------------
1 file changed, 90 deletions(-)
Signed-off-by: Jeff Garzik <[email protected]>
The bus for this was removed entirely some time ago, as well as most
of the drivers that referenced it. maple_keyb seems to have been the
odd one out, and was still sitting in the source tree (though not
actually part of the build system). Kill off the rest of it..
Signed-off-by: Paul Mundt <[email protected]>
Signed-off-by: Dmitry Torokhov <[email protected]>
While working on SH kprobes, I noticed that avr32 got the preemption
handling wrong in the no probe case. The idea is that upon entry of
kprobe_handler() preemption is disabled outright across the life of the
kprobe, only to be re-enabled in post_kprobe_handler().
However, in the event that the probe is never activated, there's never any
chance of hitting the post probe handler, which allows for the current
avr32 implementation to disable preemption indefinitely, as it's currently
missing a re-enable when no probe is activated.
Signed-off-by: Paul Mundt <[email protected]>
Cc: Haavard Skinnemoen <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Since some header inclusion paths were cleaned up, compilation
broke. Add in the headers we need directly to build again.
Signed-off-by: Paul Mundt <[email protected]>
When hugetlbpage support isn't enabled, this can be bogus.
Wrap it back in _PAGE_FLAGS_HARD to avoid changes to the
base PTE when not aiming for larger sizes.
Signed-off-by: Paul Mundt <[email protected]>
This adds a platform device for the directly connected
CF interface on R7780RP boards, for use with the
pata_platform libata driver.
Signed-off-by: Paul Mundt <[email protected]>
gcc4 gets a bit pissy about the outputs:
include/asm/atomic.h: In function 'atomic_add':
include/asm/atomic.h:37: error: invalid lvalue in asm statement
include/asm/atomic.h:30: error: invalid lvalue in asm output 1
...
this ended up being a thinko anyways, so just fix it up.
Verified for proper behaviour with the older toolchains, too.
Signed-off-by: Paul Mundt <[email protected]>
This adds basic NO_IDLE_HZ support to the SH timer API so timers
are able to wire it up. Taken from the ARM version, as it fit in
to our API with very few changes needed.
Signed-off-by: Paul Mundt <[email protected]>
This syncs up the SH clock framework with the linux/clk.h API,
for which there were only some minor changes required, namely
the clk_get() dev_id and subsequent callsites.
Signed-off-by: Paul Mundt <[email protected]>
Since all of the sys_timer sources currently do this on their own
within the ->get_offset() path, it's more sensible to just have
the caller take care of it when grabbing xtime_lock. Incidentally,
this is more in line with what others (ie, ARM) are doing already.
Signed-off-by: Paul Mundt <[email protected]>
Previously this was using a static pgd shift in the reporting
code, simply flip this to PGDIR_SHIFT which does the right
thing depending on varying PTE magnitudes on the SH-X2 MMU.
While we're at it, and since it's been recently added, use
get_TTB() for fetching the TTB, rather than the open coded
instructions.
Signed-off-by: Paul Mundt <[email protected]>
The end of the store queue bitmap is miscalculated when searching
for a free range in sq_remap(), missing the PAGE_SHIFT shift that's
done in sq_api_init(). This runs in to workloads where we can scan
beyond the end of the bitmap.
Spotted by Paul Jackson:
http://marc.theaimsgroup.com/?l=linux-kernel&m=116493191224097&w
Signed-off-by: Paul Mundt <[email protected]>
This makes the early printk support somewhat more flexible,
moving the port definition to a config option, and making the
port initialization configurable for sh-ipl+g users.
At the same time, this allows us to trivially wire up the
SH7780 SCIF0, so that's thrown in too more or less for free.
Signed-off-by: Paul Mundt <[email protected]>
There were a number of places that made evil PAGE_SIZE == 4k
assumptions that ended up breaking when trying to play with
8k and 64k page sizes, this fixes those up.
The most significant change is the way we load THREAD_SIZE,
previously this was done via:
mov #(THREAD_SIZE >> 8), reg
shll8 reg
to avoid a memory access and allow the immediate load. With
a 64k PAGE_SIZE, we're out of range for the immediate load
size without resorting to special instructions available in
later ISAs (movi20s and so on). The "workaround" for this is
to bump up the shift to 10 and insert a shll2, which gives a
bit more flexibility while still being much cheaper than a
memory access.
Signed-off-by: Paul Mundt <[email protected]>
There was a clobber issue with the register we were saving
the stack in, so we switch to a register that we handle in
the clobber list properly already.
This also follows the x86 changes for allowing the softirq
checks from hardirq context.
Signed-off-by: Paul Mundt <[email protected]>
Pass along the dev_id from request_dma() all the way down,
rather than inserting an artificial name relating to the TEI
line that we were doing before.
This makes the line a bit less obvious, but dev_id is the proper
behaviour for this regardless.
Signed-off-by: Paul Mundt <[email protected]>
Previously we linked in the ISA DMA wrapper unconditionally.
As there are very few users of this, it's better to make it
conditional.
Signed-off-by: Paul Mundt <[email protected]>
Handle the case where no registered DMACs exist somewhat more
gracefully. While we're at it, check for sysdev_create_file()
failing.
Signed-off-by: Paul Mundt <[email protected]>
This adds support for a generic push switch framework. Adaptable for
various switches, including GPIO switches and the push switches commonly
found on Renesas debug boards.
This allows switch states to be trivially reported through sysfs.
Signed-off-by: Paul Mundt <[email protected]>
Previously big endian was simply assumed if little endian was
not set, which led to some cflags ordering issues. There's not
much point to not having a big endian option, so shove one in
a choice and wire it up in the Makefile.
This lets us clean up some of the cflags ordering while we're
at it.
Signed-off-by: Paul Mundt <[email protected]>
This adds some preliminary support for the SH-X2 MMU, used by
newer SH-4A parts (particularly SH7785).
This MMU implements a 'compat' mode with SH-X MMUs and an
'extended' mode for SH-X2 extended features. Extended features
include additional page sizes (8kB, 4MB, 64MB), as well as the
addition of page execute permissions.
The extended mode attributes are placed in a second data array,
which requires us to switch to 64-bit PTEs when in X2 mode.
With the addition of the exec perms, we also overhaul the mmap
prots somewhat, now that it's possible to handle them more
intelligently.
Signed-off-by: Paul Mundt <[email protected]>
This drops the various IRQ headers that were floating around
and primarily providing hardcoded IRQ definitions for the
various CPU subtypes. This quickly got to be an unmaintainable
mess, made even more evident by the subtle breakage introduced
by the SH-2 and SH-2A changes.
Now that subtypes are able to register IRQ maps directly, just
rip all of the headers out.
Signed-off-by: Paul Mundt <[email protected]>
All of the various CPU subtypes currently hardcode TIMER_IRQ,
switch this to a config option in the few places we need this.
This allows further removal of hardcoded IRQ headers..
Signed-off-by: Paul Mundt <[email protected]>
Looking at the new syscall additions, I noticed that
sys_getcpu_wrapper wraps in to sys_tee, in what appears to be
a copy and paste error. Switch it to point to sys_getcpu..
Signed-off-by: Paul Mundt <[email protected]>
Signed-off-by: Martin Schwidefsky <[email protected]>
Currently the INTC2 code contains a fixed IRQ table that it
iterates through to set the handler type, we move this in to
the CPU subtype setup code instead and allow for submitting
the table that way.
This drops the ST40 tables, as nothing has been happening
with those processors, while converting the only existing
users to use the new table directly (SH7760 and SH7780).
Signed-off-by: Paul Mundt <[email protected]>
handle_irq_name() and set_irq_chip_and_handler() disappeared,
update for desc->name and set_irq_chip_and_handler_name() use.
Signed-off-by: Paul Mundt <[email protected]>
With the recent change ripping out interrupt_table, explicit
padding of the table was missing, causing bad things to happen
when manually inserting handlers in to the table. This problem
particularly showed up in relation to do_fpu_state_restore()
which was inserted quite deeply in to the table and ended up
scribbling over a slab object.
Signed-off-by: Paul Mundt <[email protected]>
Now with the ide.h mess sorted out, most of these boards
don't need their own directory. Move the headers out, and
update the driver paths.
Signed-off-by: Paul Mundt <[email protected]>
The driver that these were using never made it in to
drivers/ide, so kill off the rest of the cruft. These
will have to be reworked for board-specific platform
devices through libata when they're added back through
the setup code.
Signed-off-by: Paul Mundt <[email protected]>
This splits out some of the previous show_stack() implementation which
was mostly doing the show_trace() work without actually dumping any of
the stack contents. This now gets split in to two sections, where we
do the fetching of the stack pointer and subsequent stack dumping in
show_stack(), while moving the call trace in to show_trace().
Signed-off-by: Paul Mundt <[email protected]>
Kill off interrupt_table for all of the CPU subtypes, we now
default in to stepping in to do_IRQ() for _all_ IRQ exceptions
and counting the spurious ones, rather than simply flipping on
the ones we cared about. This and enabling the IRQ by default
automatically has already uncovered a couple of bugs and IRQs
that weren't being caught, as well as some that are being
generated far too often (SCI Tx Data Empty, for example).
The general rationale is to use a marker for interrupt exceptions,
test for it in the handle_exception() path, and skip out to
do_IRQ() if it's found. Everything else follows the same behaviour
of finding the cached EXPEVT value in r2/r2_bank, we just rip out
the INTEVT read from entry.S entirely (except for in the kGDB NMI
case, which is another matter).
Note that while this changes the do_IRQ() semantics regarding r4
handling, they were fundamentally broken anyways (relying entirely
on r2_bank for the cached code). With this, we do the INTEVT read
from do_IRQ() itself (in the CONFIG_CPU_HAS_INTEVT case), or fall
back on r4 for the muxed IRQ number, which should also be closer
to what SH-2 and SH-2A want anyways.
Signed-off-by: Paul Mundt <[email protected]>
Now that we've started accounting for spurious IRQs, change the
logic somewhat so that we have a better chance of catching them.
Signed-off-by: Paul Mundt <[email protected]>
At the moment we wrap GENERIC_TIME around our existing timer API.
As boards start providing their own clocksources, they're able to
select GENERIC_TIME accordingly and optimize out most of the timer
API.
Once the current timers have been reworked as proper clocksource
drivers, the rest of the place holders for the timer API can go
away and we can flip on GENERIC_TIME unconditionally.
Signed-off-by: Paul Mundt <[email protected]>
generic__raw_read_trylock() was broken, fix up the __raw_read_trylock()
implementation for something sensible. Taken from m32r, which has the
same use cases.
Signed-off-by: Paul Mundt <[email protected]>
Paul Mundt