BackPup/Linux
1
0 Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-10-07 05:31:08 -04:00
Code Issues Packages Projects Releases Wiki Activity
1,088,684 Commits 1 Branch 949 Tags
e4d755cfec44197f605e1a2e9ff17434c6c9d513
Commit Graph
1088684 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Yoshihiro Shimoda e4d755cfec arm64: dts: renesas: Add Renesas White Hawk boards support 
Initial support for the Renesas White Hawk CPU and BreakOut boards.

Signed-off-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-05-06 11:09:10 +02:00
Yoshihiro Shimoda 987da486d8 arm64: dts: renesas: Add Renesas R8A779G0 SoC support 
Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC.

Signed-off-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-05-06 11:09:10 +02:00
Geert Uytterhoeven a4744a1de6 Merge tag 'renesas-r8a779g0-dt-binding-defs-tag' into renesas-arm-dt-for-v5.19 
Renesas R-Car V4H DT Binding Definitions

Clock and Power Domain definitions for the Renesas R-Car V4H (R8A779G0)
SoC, shared by driver and DT source files.
 2022-04-29 12:22:36 +02:00
Biju Das 3f67af66e6 arm64: dts: renesas: rzg2ul-smarc-som: Enable watchdog 
Enable watchdog{0,2} interfaces on RZ/G2UL SMARC EVK.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-29 09:42:17 +02:00
Biju Das 0b3e18dbcd arm64: dts: renesas: rzg2ul-smarc-som: Enable OSTM 
Enable OSTM{1, 2} interfaces on RZ/G2UL SMARC EVK.
OSTM0 is reserved for TF-A.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-29 09:42:17 +02:00
Biju Das 820e976909 arm64: dts: renesas: rzg2ul-smarc: Enable CANFD 
Enable CANFD on RZ/G2UL SMARC platform.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-29 09:42:17 +02:00
Biju Das b0fa698b83 arm64: dts: renesas: rzg2ul-smarc: Enable i2c{0,1} and wm8978 
Enable i2c{0,1} on RZ/G2UL SMARC EVK by deleting respective
entries from board dts and adding pincontrol entries to the
soc-pinctrl dtsi. Also enable wm8978 audio codec.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-29 09:41:59 +02:00
Biju Das a8352a5158 arm64: dts: renesas: r9a07g043: Fillup the WDT{0,2} stub nodes 
Fillup the WDT{0,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-28 16:51:33 +02:00
Biju Das e42faad1ef arm64: dts: renesas: r9a07g043: Fillup the OSTM{0,1,2} stub nodes 
Fillup the OSTM{0,1,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-28 16:51:33 +02:00
Biju Das 1de1b44833 arm64: dts: renesas: r9a07g043: Fillup the CANFD stub node 
Fillup the CANFD stub node in RZ/G2UL (R9A07G043) SoC DTSI.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-28 16:51:33 +02:00
Biju Das f52e14095e arm64: dts: renesas: r9a07g043: Add USB2.0 support 
Add USB2.0 host and device support by filling usb phy control,
phy, device and host stub nodes in RZ/G2UL SoC dtsi.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-28 16:51:32 +02:00
Biju Das 559f2b0708 arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node 
Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/G2UL
(R9A07G043) SoC DTSI.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-28 16:51:32 +02:00
Biju Das bc9e1dbb17 arm64: dts: renesas: r9a07g043: Add I2C2 node and fillup the I2C{0,1,3} stub nodes 
Add I2C2 node and fillup the I2C{0,1,3} stub nodes in RZ/G2UL
(R9A07G043) SoC DTSI.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-28 16:51:32 +02:00
Herve Codina ed66b37f91 ARM: dts: r9a06g032: Add missing '#power-domain-cells' 
Without '#power-domain-cells' property, power-domains cannot
be used. This property is noted required in the device-tree
binding.

Add '#power-domain-cells' as needed.

Signed-off-by: Herve Codina <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-28 16:50:51 +02:00
Yoshihiro Shimoda f2afa78d5a dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions 
Add all Clock Pulse Generator Core Clock Outputs for the Renesas
R-Car V4H (R8A779G0) SoC.

Signed-off-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-25 10:34:19 +02:00
Yoshihiro Shimoda 90715507cb dt-bindings: power: Add r8a779g0 SYSC power domain definitions 
Add power domain indices for R-Car V4H (r8a779g0).

Signed-off-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-25 10:34:19 +02:00
Geert Uytterhoeven aa70cbda74 ARM: dts: r9a06g032: Drop "arm,cortex-a7-timer" from timer node 
"make dtbs_check":

    arch/arm/boot/dts/r9a06g032-rzn1d400-db.dt.yaml: timer: compatible: 'oneOf' conditional failed, one must be fixed:
	    ['arm,cortex-a7-timer', 'arm,armv7-timer'] is too long
	    'arm,cortex-a7-timer' is not one of ['arm,cortex-a15-timer']
	    'arm,cortex-a7-timer' is not one of ['arm,armv7-timer']
	    'arm,cortex-a7-timer' is not one of ['arm,armv8-timer']
	    From schema: Documentation/devicetree/bindings/timer/arm,arch_timer.yaml

The Cortex-A7 timer should just declare compatibility with
"arm,armv7-timer".

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/a8e0cf00a983b4c539cdb1cfad5cc6b10b423c5b.1649680220.git.geert+renesas@glider.be
 2022-04-19 10:27:36 +02:00
Geert Uytterhoeven 8ba8560d4f arm64: dts: renesas: r8a779f0: Add GPIO nodes 
Add device nodes for the General Purpose Input/Output (GPIO) blocks on
the Renesas R-Car S4-8 (R8A779F0) SoC.

Note that GPIO blocks 4-7 are not added, as they can only be accessed
from the Control Domain.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/7fb68561026fa8bb5d9baf0596560c5c719a38cc.1649086225.git.geert+renesas@glider.be
 2022-04-19 10:27:36 +02:00
Biju Das 6494e4f905 arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platform 
Enable Ethernet{0,1} interfaces on RZ/G2UL SMARC EVK.

Ethernet0 pins are muxed with CAN0, CAN1, SSI1 and RSPI1 pins and Ethernet0
device selection is based on the SW1[3] switch position.

Set SW1[3] to position OFF for selecting CAN0, CAN1, SSI1 and RSPI1.
Set SW1[3] to position ON for selecting Ethernet0.

This patch disables Ethernet0 on RZ/G2UL SMARC platform by default.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:56:09 +02:00
Biju Das ed8efe50b7 arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC on SMARC platform 
RZ/G2UL SoM has both 64GB eMMC and microSD connected to SDHI0.

Both these interfaces are mutually exclusive and the SD0 device
selection is based on SW1[2] on SoM module.

Set SW1[2] to position OFF for selecting eMMC
Set SW1[2] to position ON for selecting microSD

This patch enables eMMC on RZ/G2UL SMARC platform by default.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:56:09 +02:00
Biju Das a74a0bf3f3 arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platform 
Enable the microSD card slot connected to SDHI1 on the RZ/G2UL SMARC
platform by removing the sdhi1 override which disabled it, and by adding
the necessary pinmux required for SDHI1.

This patch also adds gpios property to vccq_sdhi1 regulator.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:56:09 +02:00
Biju Das 13ea8b3584 arm64: dts: renesas: r9a07g043: Add GbEthernet nodes 
Add Gigabit Ethernet{0,1} nodes to SoC DTSI.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:56:09 +02:00
Biju Das 20e63d3948 arm64: dts: renesas: r9a07g043: Add SDHI nodes 
Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:56:09 +02:00
Biju Das 4e44055440 arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pins 
Add scif0 and audio clk pins to soc pinctrl dtsi and drop deleting
the pinctrl-0 and pinctrl-names properties for scif0 node so that
we now actually make use of these properties for scif0.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:56:09 +02:00
Biju Das 2d10555298 arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub node 
Fillup the pinctrl(GPIO) stub node in RZ/G2UL SoC DTSI.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:56:09 +02:00
Biju Das 895199bc4e arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK 
Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11):
- memory
- External input clock
- CPG
- DMA
- SCIF

It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which are not tested and delete the
corresponding pinctrl definitions.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:56:09 +02:00
Biju Das cf40c9689e arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC 
Add initial DTSI for RZ/G2UL SoC.

Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share
the common dtsi (rz-smarc.dtsi) file. Place holders are added in
device nodes to avoid compilation errors for the devices which have
not been enabled yet on RZ/G2UL SoC.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:56:09 +02:00
Geert Uytterhoeven 0faf567d6d Merge tag 'renesas-r9a07g043-dt-binding-defs-tag' into HEAD 
Renesas RZ/G2UL DT Binding Definitions

Clock and reset definitions for the Renesas RZ/G2UL (R9A07G043) SoC,
shared by driver and DT source files.
 2022-04-13 13:56:04 +02:00
Biju Das f40846e7c9 arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1 from common dtsi 
On RZ/G2{L,LC} SoM module, gpio for power selection is connected to
P39_1 whereas on RZ/G2UL it is connected to P6_1. So move gpios property
of vccq_sdhi1 regulator from common dtsi to soc specific dtsi.

Signed-off-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:54:32 +02:00
Biju Das 061ba41c74 arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board 
RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the
carrier board.  This patch adds pinmux and spi1 nodes to the carrier
board dtsi file and drops deleting pinctl* properties from DTS file.

RSPI1 interface is tested by setting the macro SW_RSPI_CAN to 0.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:53:42 +02:00
Geert Uytterhoeven 79e903fbf4 arm64: dts: renesas: ulcb: Add RPC HyperFlash device node 
Add the RPC HyperFlash device node along with its partitions to the
common ULCB board DTS file.

Based on a patch in the BSP by Valentine Barshak.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/61a63e819d4296760ca7ae83ef5226a2c4d7bd93.1648548339.git.geert+renesas@glider.be
 2022-04-13 13:53:42 +02:00
Geert Uytterhoeven 1ee6674bbe arm64: dts: renesas: salvator-common: Add RPC HyperFlash device node 
Add the RPC HyperFlash device node along with its partitions to the
common Salvator-X(S) board DTS file.

Based on a patch in the BSP by Valentine Barshak.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/cfc6af8a4c42febcc405b7356c38448eec8e29b0.1648548339.git.geert+renesas@glider.be
 2022-04-13 13:53:42 +02:00
Geert Uytterhoeven 5f300a7f39 arm64: dts: renesas: ebisu: Add RPC HyperFlash device node 
Add the RPC HyperFlash device node along with its partitions to the
common Ebisu board DTS file.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/b14c769f62211b67d90dbd2f127357756e6cb4fa.1648548339.git.geert+renesas@glider.be
 2022-04-13 13:53:42 +02:00
Geert Uytterhoeven a1de91f0ac arm64: dts: renesas: draak: Add RPC HyperFlash device node 
Add the RPC HyperFlash device node along with its partitions to the
common Draak board DTS file.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/0f3d3018ecfcdce1bce67708708a6d3a98368b10.1648548339.git.geert+renesas@glider.be
 2022-04-13 13:53:42 +02:00
Geert Uytterhoeven f191fba769 arm64: dts: renesas: rcar-gen3: Add RPC device nodes 
Add device nodes for the SPI Multi I/O Bus Controllers (RPC-IF) on the
various R-Car Gen3 SoCs that do not have support for them yet in their
device trees (R-Car H3, M3-W, M3-W+, M3-N, E3, and D3).

Based on patches in the BSP by Valentine Barshak.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/3231749c7b63df1a2134daabe66446a3e0e5515b.1648548339.git.geert+renesas@glider.be
 2022-04-13 13:53:42 +02:00
Wolfram Sang ccc0dd722e arm64: dts: renesas: rcar-gen4: Add interrupt properties to watchdog nodes 
Driver doesn't use it yet, but let's describe the HW properly.

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:43:04 +02:00
Wolfram Sang 7ac8afba22 arm64: dts: renesas: rzg2: Add interrupt properties to watchdog nodes 
Driver doesn't use it yet, but let's describe the HW properly.

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:43:04 +02:00
Wolfram Sang 2bc0aa18ee arm64: dts: renesas: rcar-gen3: Add interrupt properties to watchdog nodes 
Driver doesn't use it yet, but let's describe the HW properly.

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:43:04 +02:00
Wolfram Sang cb97d48555 ARM: dts: rzg1: Add interrupt properties to watchdog nodes 
Driver doesn't use it yet, but let's describe the HW properly.

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:43:03 +02:00
Wolfram Sang 2e4d5fd6f5 ARM: dts: rcar-gen2: Add interrupt properties to watchdog nodes 
Driver doesn't use it yet, but let's describe the HW properly.

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 13:43:03 +02:00
Biju Das eb27897854 dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions 
Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
0.51, Nov. 2021).

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-13 12:21:04 +02:00
Geert Uytterhoeven 599fdfddc8 arm64: dts: renesas: spider: Add Ethernet sub-board 
Add a DTS file for the Spider Ether TSN sub-board (RTP8A779F0ASKB0ST0S),
and include it from the main r8a779f0-spider.dts.

For now its contents are limited to the Board ID EEPROM.

Extracted from a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/5aa58816182b34d9e5795bc1e22784f4e4879d13.1643898884.git.geert+renesas@glider.be
 2022-04-11 12:00:33 +02:00
Geert Uytterhoeven b74d5d65af arm64: dts: renesas: spider-cpu: Add I2C4 and EEPROMs 
Enable the I2C4 bus on the Falcon CPU board, and describe the I2C EEPROMs
present on the Spider CPU and BreakOut boards.

Extracted from a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/6d8917e49f83b6a932970ca169100eb086d11f16.1643898884.git.geert+renesas@glider.be
 2022-04-11 12:00:32 +02:00
Geert Uytterhoeven bd04437341 arm64: dts: renesas: r8a779f0: Add I2C nodes 
Add device nodes for the I2C Bus Interfaces on the Renesas R-Car S4-8
(R8A779F0) SoC.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/e1c7fb17801bc82a74aa5364212d02ba51535dd2.1643898884.git.geert+renesas@glider.be
 2022-04-11 12:00:32 +02:00
Koji Matsuoka 0182581a9f arm64: dts: renesas: r8a77961: Add CAN-FD node 
Add the device node for the CAN-FD device on R-Car M3-W+.

Signed-off-by: Koji Matsuoka <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-04 11:06:56 +02:00
Ulrich Hecht d2194187aa arm64: dts: renesas: falcon: Enable CANFD 0 and 1 
Enables confirmed-working CAN interfaces 0 and 1 on the Falcon board.

Signed-off-by: Ulrich Hecht <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-04 11:06:56 +02:00
Ulrich Hecht d63833b869 arm64: dts: renesas: r8a779a0: Add CANFD device node 
This patch adds a CANFD device node for r8a779a0.

Based on patch by Kazuya Mizuguchi.

Signed-off-by: Ulrich Hecht <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-04 11:06:56 +02:00
Kieran Bingham 9a4259e596 arm64: dts: renesas: falcon-cpu: Use INTC_EX for SN65DSI86 
The INTC block is a better choice for handling the interrupts on the V3U
as the INTC will always be powered, while the GPIO block may be
de-clocked if not in use. Further more, it may be likely to have a lower
power consumption as it does not need to drive the pins.

Switch the interrupt parent and interrupts definition from gpio1 to
irq0 on intc_ex, and configure the PFC accordingly.

Signed-off-by: Kieran Bingham <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-04 11:06:56 +02:00
Lad Prabhakar f6a2f28ab1 arm64: dts: renesas: r9a07g054: Add TSU node 
Add TSU and thermal-zones nodes to RZ/V2L (R9A07G054) SoC DTSI.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-04 11:06:56 +02:00
Lad Prabhakar 4b7e7f1083 arm64: dts: renesas: r9a07g054: Add OPP table 
Add OPP table for RZ/V2L SoC.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
 2022-04-04 11:06:55 +02:00