* Fix IRQ support in the 85xx CDS boards so it uses the new
generic stuff
* Fix PCI IRQ mapping to use the device tree
* Disabled i8259 support to allow the CDS to boot. This will be
fixed soon, but the current code doesn't even compile, so this
is a vast improvement
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Paul Mackerras <[email protected]>
* Fixed 8540 ADS support for the new irq layer
* Fixed 8540 ADS support for mapping PCI interrupts
* Updated 8540 ADS to use device tree for interrupt assignment
and sense values
Signed-off-by: Paul Mackerras <[email protected]>
This patch fixes several bugs in the gianfar driver, including a major one
where spinlocks were horribly broken:
* Split gianfar locks into two types: TX and RX
* Made it so gfar_start() now clears RHALT
* Fixed a bug where calling gfar_start_xmit() with interrupts off would
corrupt the interrupt state
* Fixed a bug where a frame could potentially arrive, and never be handled
(if no more frames arrived
* Fixed a bug where the rx_work_limit would never be observed by the rx
completion code
* Fixed a bug where the interrupt handlers were not actually protected by
their spinlocks
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
This patch adds support for 85xx CDS support to arch/powerpc
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Add PCI support for setting PCI from flat device tree on 85xx specifically for
MPC8540 ADS.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
This patch adds oprofile support for the 7450 and all its multitudinous
derivatives.
* Added 7450 (and derivatives) support for oprofile
* Changed e500 cputable to have oprofile model and cpu_type fields
* Added support for classic 32-bit performance monitor interrupt
* Cleaned up common powerpc oprofile code to be as common as possible
* Cleaned up oprofile_impl.h to reflect 32 bit classic code
* Added 32-bit MMCRx bitfield definitions and SPR numbers
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Paul Mackerras <[email protected]>
This seems to have gotten lost, so I'll resend.
Signed-off-by: Andy Fleming <[email protected]>
* Added sysfs support to gianfar for modifying FIFO and stashing parameters
* Updated driver to support 10 Mbit, full duplex operation
* Improved comments throughout
* Cleaned up and optimized offloading code
* Fixed a bug where rx buffers were being improperly mapped and unmapped
* (only manifested if cache-coherency was off)
* Added support for using the eTSEC exact-match MAC registers
* Bumped the version to 1.3
* Added support for distinguishing between reduced 100 and 10 Mbit modes
* Modified default coalescing values to lower latency
* Added documentation
Signed-off-by: Jeff Garzik <[email protected]>
This patch adds back the code that was taken out, thus re-enabling:
* The PHY Layer to initialize without crashing
* Drivers to actually connect to PHYs
* The entire PHY Control Layer
This patch is used by the gianfar driver, and other drivers which are in
development.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
ethernet drivers to remain as ignorant as is reasonable of the connected
PHY's design and operation details.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
Andy Fleming