I believe support was disabled due to issues with earlier versions of
the board/processor. At worst, adding the ports back into the device
tree should result in enabling ports that don't work on older systems,
so the default should be to enable them.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
When gracefully stopping the controller, the driver was continuing if
*either* RX or TX had stopped. We need to wait for both, or the
controller could get into an invalid state.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
gianfar needed to ensure existence of the *skbuff arrays before
freeing the skbs in them, rather than ensuring their nonexistence.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
commit 1577ecef76
Author: Andy Fleming <[email protected]>
Date: Wed Feb 4 16:42:12 2009 -0800
netdev: Merge UCC and gianfar MDIO bus drivers
left out the deletion of gianfar_mii.c.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Stashing is only supported on the 85xx (e500-based) SoCs. The 83xx and 86xx
chips don't have a proper cache for this. U-Boot has been updated to add
stashing properties to the device tree nodes of gianfar devices on 85xx. So
now we modify Linux to keep stashing off unless those properties are there.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
The MDIO bus drivers for the UCC and gianfar ethernet controllers are
essentially the same. There's no reason to duplicate that much code.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
SOFT_RESET must be asserted for at least 3 TX clocks in order for it to work
properly. The syncs in the gfar_write() commands have been hiding this, but
we need to guarantee it.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
BD_LENGTH_MASK is supposed to catch the low 16-bits of the status field, not
the low byte. The old way, we would never be able to clean up tx packets with
sizes divisible by 256.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
gfar_poll would declare polling done once the rx queue was empty,
but the tx queue could still have packets left.
Stolen mostly from the e1000 driver.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
The patch which fixed gianfar so it drops packets when it runs out
of memory left in the code which frees the skb when it drops packets.
Change the code so that we only free the skb if the new skb was successfully
created.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
genphy_setup_forced hasn't actually reset the PHY for a long time,
but a comment to that effect remained in the code, so code continued
to act as if it *had* reset the PHY, and called the necessary fixup
functions to respond to a PHY reset. With no reset, those functions
are no longer needed, so we remove them.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
This code is based strongly on code from Dai Haruki <[email protected]>.
The gianfar Buffer Descriptors are arranged in a circular array, the end of
which is denoted by setting the "WRAP" bit in the descriptor. However, the
software knows the end of the ring because it knows how many descriptors are
there. Rather than check each descriptor for whether the WRAP bit is set,
use pointer math to determine where the next BD is. This is also useful for
when we want to look at BDs other than the very next one (for Scatter-Gather).
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Does the same for the accompanying MDIO driver, and then modifies the TBI
configuration method. The old way used fields in einfo, which no longer
exists. The new way is to create an MDIO device-tree node for each instance
of gianfar, and create a tbi-handle property to associate ethernet controllers
with the TBI PHYs they are connected to.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
gfar_halt does everything we want to do there, including disabling
TX/RX. It also doesn't unnecessarily enable DMA if it's already
stopped.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
We weren't unmapping DMA memory, which will break when gianfar gets used
on systems with more than 32-bits of memory. Also, it's just plain wrong.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
Mostly having to do with not marking things __iomem. And some failure
to use appropriate accessors to read MMIO regs.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
The old code assumed there was only one, but the 8572 actually has 3.
Also, our usual id, 0xe0024520, gets resolved to -1 somewhere, and this was
preventing the multiple buses from having different ids. So we only keep
the low 20 bits, which have the interesting info, anyway.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
We were passing NULL as the device. When we actually start supporting
more interesting memory configurations, this will break things, so
we proactively are fixing the bug.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
The 8568 MDS needs some configuration changes to the PHY in order to
work properly. These are done in the firmware, normally, but Linux
shouldn't need to rely on the firmware running such things (someone
could disable the PHY support in the firmware to save space, for instance).
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
The loop that unmaps all of the TX Buffer Descriptors never actually
moves the txbd pointer, so we were just repeatedly unmapping the first one.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
ucc_geth didn't have anything marked as __iomem. It was also inconsistent
with its use of in/out accessors (using them sometimes, not using them other
times). Cleaning this up cuts the warnings down from hundreds to just over a
dozen.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
Declared some things static, declared some things in the header.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
During sparse cleanup, found a locking bug. Some of the sysfs functions were
acquiring a lock, and then returning in the event of an error. We rearrange
the code so that the lock is released in error conditions, too.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
gianfar was unable to handle failed skb allocation for rx buffers, so
we were spinning until it succeeded. Actually, it was worse--we were
spinning for a long time, and then silently failing. Instead, we take
Stephen Hemminger's suggestion to try the allocation earlier, and drop the
packet if it failed.
We also make a couple of tweaks to how buffer descriptors are set up.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
Sometimes the specific interaction between the platform and the PHY
requires special handling. For instance, to change where the PHY's
clock input is, or to add a delay to account for latency issues in the
data path. We add a mechanism for registering a callback with the PHY
Lib to be called on matching PHYs when they are brought up, or reset.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
The patch that changed mdio_bus to a string didn't conflict strongly enough
with the patch that added fixed PHY support to UCC. Gather it back into
the fold.
Fixes this error:
...
CC drivers/net/ucc_geth.o
'ucc_geth_probe':
/home/bunk/linux/kernel-2.6/git/linux-2.6/drivers/net/ucc_geth.c:3935: error:
incompatible types in assignment
make[3]: *** [drivers/net/ucc_geth.o] Error 1
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
Having the id field be an int was making more complex bus topologies
excessively difficult. For now, just convert it to a string, and
change all instances of "bus->id = val" to
snprintf(id, MII_BUS_ID_LEN, "%x", val).
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
- Fix Rx/Tx HW interrupt coalescing counter reset logic. Disabling
is required before resetting the counter.
- Update the Default both Rx and Tx coalescing timer
threshold. Formerly 4 is set which is equal to 1.5 frame at the line
rate of 1GbE interface, and it doesn't match to the coalescing frame
count which is set to 16. Threashold 21 is matched to frame count 16.
Signed-off-by: Dai Haruki <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
If the LAST bit is not set in the RxBD, it's possible we're processing
an incomplete frame, which is bad. While we're at it, add a constant
for the error bitmask, so the whole if-clause fits on one line,
and is more legible.
Signed-off-by: Dai Haruki <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
Not all e300 cores support the performance monitors, and the ones
that don't will be confused by the mf/mtpmr instructions. This
allows the support to be optional, so the 8349 can turn it off
while the 8379 can turn it on. Sadly, those aren't config options,
so it will be left to the defconfigs and the users to make that
determination.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
The PHY Lib now uses mutexes instead of spin_locks. ucc_geth
and gianfar both grab the locks in their mdio_reset functions,
so they need to use mutex_(un)lock instead. This was not caught
until someone tested it on an SMP system.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
The e300 c3 and c4 variants support hardware performance monitor counters
which are identical to those found in the e500.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Some of the more recent e300 cores have the same performance monitor
implementation as the e500. e300 isn't book-e, so the name isn't
really appropriate. In preparation for e300 support, rename a bunch
of fsl_booke things to say fsl_emb (Freescale Embedded Performance Monitors).
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
phy_read() returns a negative number if there's an error, but the
error-checking code in the Vitesse driver's config_intr function
triggers if phy_read() returns non-zero. Correct that.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
The TSEC/eTSEC can detect the interface to the PHY automatically,
but it isn't able to detect whether the RGMII connection needs internal
delay. So we need to detect that change in the device tree, propagate
it to the platform data, and then check it if we're in RGMII. This fixes
a bug on the 8641D HPCN board where the Vitesse PHY doesn't use the delay
for RGMII.
Signed-off-by: Andy Fleming <[email protected]>
The Vitesse PHY on the 8641D needs to be set up with internal delay to
work in RGMII mode. So we add skew when it is set to RGMII_ID mode.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Haruki Dai <[email protected]>
Signed-off-by: Haiying Wang <[email protected]>
The TSEC/eTSEC automatically detect their PHY interface type, unless
the type is RGMII-ID (RGMII with internal delay). In that situation,
it just detects RGMII. In order to fix this, we need to pass in rgmii-id
if that is the connection type.
Signed-off-by: Andy Fleming <[email protected]>
The Vitesse 824x PHY doesn't allow an interrupt to be cleared if
the mask bit for that interrupt isn't set. This means that the PHY
Lib's order of handling interrupts (disable, then clear) breaks on this
PHY. However, clearing then disabling the interrupt opens up the code
for a silly race condition. So rather than change the PHY Lib, we change
the Vitesse driver so it always clears interrupts before disabling them.
Further, the ack function only clears the interrupt if interrupts are
enabled.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: York Sun <[email protected]>
Acked-by: Haiying Wang <[email protected]>
Changes include:
* New support for 88e1145
* New support for 88e111s
* Fixing 88e1101 driver to not match non-88e1101 PHYs
* Increases in feature support across Marvell PHY product line
* Fixes a bunch of whitespace issues found by Lindent
Signed-off-by: Andrew Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
Most PHYs connect to an ethernet controller over a GMII or MII
interface. However, a growing number are connected over
different interfaces, such as RGMII or SGMII.
The ethernet driver will tell the PHY what type of connection it
is by setting it manually, or passing it in through phy_connect
(or phy_attach).
Changes include:
* Updates to documentation
* Updates to PHY Lib consumers
* Changes to PHY Lib to add interface support
* Some minor changes to whitespace in phy.h
* gianfar driver now detects interface and passes appropriate
value to PHY Lib
Signed-off-by: Andrew Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
This patch requires the new support for configurable PHY
interfaces.
Changes include:
* New support for 88e1145
* New support for 88e111s
* Fixing 88e1101 driver to not match non-88e1101 PHYs
* Increases in feature support across Marvell PHY product line
* Fixes a bunch of whitespace issues found by Lindent
Signed-off-by: Andrew Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
* genphy_update_link is now exported
* Added a fix from [email protected] which changes forcing so it
only updates the link. Otherwise, it never tries the lower
values, since it is always overwriting the speed/duplex values
with the current ones, rather than the intended ones.
* Fixed a bug where bringing up a PHY with no link caused it to
timeout, and enter forcing mode. Once in forcing mode,
plugging in the link didn't autonegotiate. Now the AN state
detects the lack of link, and enters the NO_LINK state. AN
only times out if the link is up and AN fails
* Cleaned up the PHY_AN case, reducing one level of indentation
for the timeout code.
Signed-off-by: Jeff Garzik <[email protected]>
Mostly this is to allow for error checking (check the return for NO_IRQ)
Added a check that the resource is non-NULL, too.
Signed-off-by: Andrew Fleming <[email protected]>
Acked-by: Benjamin Herrenschmidt <[email protected]>
Signed-off-by: Paul Mackerras <[email protected]>
* Cleaned up interrupt mapping a little by adding a helper
function which parses the irq out of the device-tree, and puts
it into a resource.
* Changed the arch/ppc platform files to specify PHY_POLL, instead of -1
* Changed the fixed phy to use PHY_IGNORE_INTERRUPT
* Added ethtool.h and mii.h to phy.h includes
Signed-off-by: Paul Mackerras <[email protected]>
Fixed a compile error in building the 85xx support with oprofile, and in
the process cleaned up some issues with the fsl_booke performance monitor
code.
* Reorganized FSL Book-E performance monitoring code so that the 7450
wouldn't be built if the e500 was, and cleaned it up so it was more
self-contained.
* Added a cpu_setup function for FSL Book-E. The original
cpu_setup function prototype had no arguments, assuming that
the reg_setup function would copy the required information into
variables which represented the registers. This was silly for
e500, since it has 1 register per counter (rather than 3 for
all counters), so the code has been restructured to have
cpu_setup take the current counter config array as an argument,
with op_powerpc_setup() invoking op_powerpc_cpu_setup() through
on_each_cpu(), and op_powerpc_cpu_setup() invoking the
model-specific cpu_setup function with an argument. The
argument is ignored on all other platforms at present.
* Fixed a confusing line where a trinary operator only had two
arguments
Signed-off-by: Andrew Fleming <[email protected]>
Signed-off-by: Paul Mackerras <[email protected]>
The e500 core generates an illegal instruction exception when it tries
to execute the lwsync instruction, which we currently use for rmb().
This fixes it by using the LWSYNC macro, which turns into a plain sync
on 32-bit machines.
Signed-off-by: Andrew Fleming <[email protected]>
Signed-off-by: Paul Mackerras <[email protected]>
The original problem that inspired this patch was solved quite some time
ago (Turning off PCI didn't work), but this patch neatens things up a
little (I think), by putting all the PCI stuff inside a single CONFIG_PCI
block. It also removes the OF PCI bus matching entries if CONFIG_PCI is
off.
Signed-off-by: Paul Mackerras <[email protected]>
* Fix IRQ support in the 85xx CDS boards so it uses the new
generic stuff
* Fix PCI IRQ mapping to use the device tree
* Disabled i8259 support to allow the CDS to boot. This will be
fixed soon, but the current code doesn't even compile, so this
is a vast improvement
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Paul Mackerras <[email protected]>
* Fixed 8540 ADS support for the new irq layer
* Fixed 8540 ADS support for mapping PCI interrupts
* Updated 8540 ADS to use device tree for interrupt assignment
and sense values
Signed-off-by: Paul Mackerras <[email protected]>
This patch fixes several bugs in the gianfar driver, including a major one
where spinlocks were horribly broken:
* Split gianfar locks into two types: TX and RX
* Made it so gfar_start() now clears RHALT
* Fixed a bug where calling gfar_start_xmit() with interrupts off would
corrupt the interrupt state
* Fixed a bug where a frame could potentially arrive, and never be handled
(if no more frames arrived
* Fixed a bug where the rx_work_limit would never be observed by the rx
completion code
* Fixed a bug where the interrupt handlers were not actually protected by
their spinlocks
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
This patch adds support for 85xx CDS support to arch/powerpc
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Add PCI support for setting PCI from flat device tree on 85xx specifically for
MPC8540 ADS.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
This patch adds oprofile support for the 7450 and all its multitudinous
derivatives.
* Added 7450 (and derivatives) support for oprofile
* Changed e500 cputable to have oprofile model and cpu_type fields
* Added support for classic 32-bit performance monitor interrupt
* Cleaned up common powerpc oprofile code to be as common as possible
* Cleaned up oprofile_impl.h to reflect 32 bit classic code
* Added 32-bit MMCRx bitfield definitions and SPR numbers
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Paul Mackerras <[email protected]>
This seems to have gotten lost, so I'll resend.
Signed-off-by: Andy Fleming <[email protected]>
* Added sysfs support to gianfar for modifying FIFO and stashing parameters
* Updated driver to support 10 Mbit, full duplex operation
* Improved comments throughout
* Cleaned up and optimized offloading code
* Fixed a bug where rx buffers were being improperly mapped and unmapped
* (only manifested if cache-coherency was off)
* Added support for using the eTSEC exact-match MAC registers
* Bumped the version to 1.3
* Added support for distinguishing between reduced 100 and 10 Mbit modes
* Modified default coalescing values to lower latency
* Added documentation
Signed-off-by: Jeff Garzik <[email protected]>
This patch adds back the code that was taken out, thus re-enabling:
* The PHY Layer to initialize without crashing
* Drivers to actually connect to PHYs
* The entire PHY Control Layer
This patch is used by the gianfar driver, and other drivers which are in
development.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
ethernet drivers to remain as ignorant as is reasonable of the connected
PHY's design and operation details.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
Andy Fleming