The config transactions "scheduler" was hopelessly broken,
repeating completed transaction instead of picking up
next pending one.
Fixed now. Also improved debug messages.
Signed-off-by: Pawel Moll <[email protected]>
Reviewed-by: Jon Medhurst <[email protected]>
Signed-off-by: Samuel Ortiz <[email protected]>
This patch adds the DTS files for the ARMv8 RTSM and Foundation models.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Factor out the SP810 clocking code into a separate driver,
selecting better (faster) parent at clk_prepare() time.
This is to avoid problems with clocking infrastructure
initialisation order, in particular to avoid dependency
of fixed clock being initialized before SP810. It also
makes vexpress platform OF-based clock initialisation code
unnecessary.
Signed-off-by: Pawel Moll <[email protected]>
Tested-by: Catalin Marinas <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
[[email protected]: add .unprepare, FIXME comment, cleaned up code]
The ARM perf core code used to rely on the pmu node being
compatible with "arm,cortex-a9-pmu", even when the PMUs
of the different Cortex-A processors are not really
compatible... This is no longer required and actually
became harmful, so remove all the offending values
from Versatile Express DTS files.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
The registration of the "leds-gpio" device was using
"vexpress_sysreg_dev" as a parent before it was actually
set to something different than NULL.
Trivial fix by reordering the code.
Reported-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Samuel Ortiz <[email protected]>
The LEDs on the Versatile Express motherboard are controlled
through simple memory-mapped register. This patch extends
the pseudo-GPIO controller definition for these lines and
creates generic "leds-gpio" device using them
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Samuel Ortiz <[email protected]>
The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
and v116/216) contains a modified version of the PL180 MMCI, with
PeriphID Configuration value changed to 0x2.
This version adds an optional "hardware flow control" feature. When
enabled MMC card clock will be automatically disabled when FIFO is
about to over/underflow and re-enabled once the host retrieved some
data. This makes the controller immune to over/underrun errors caused
by big interrupt handling latencies.
This patch adds relevant device variant in the driver.
Signed-off-by: Pawel Moll <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Acked-by: Ulf Hansson <[email protected]>
Signed-off-by: Russell King <[email protected]>
The vexpress-sysreg driver does not have to be initialized
early, when the platform doesn't require this. Unfortunately
in such case it wasn't initialized correctly - master site
lookup and config bridge registration were missing. Fixed now.
Signed-off-by: Pawel Moll <[email protected]>
As the kernel is able to cope with multiple clusters,
uncomment the A7 cores in the Device Tree for V2P-CA15_A7
tile, making all 5 cores available to the user.
Signed-off-by: Pawel Moll <[email protected]>
When the resource_size_t is 64-bit long, the sscanf() on
the virtio device command line paramter string may return
wrong value because its format was defined as "%u". Fixed
by using an intermediate local value of a known length.
Also added cleaned up the resource creation and added extra
comments to make the parameters parsing easier to follow.
Reported-by: Lee Jones <[email protected]>
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Rusty Russell <[email protected]>
The .notes, being read-only data by nature, were placed between
read-write .data and .bss. This was harmful in case of the XIP
kernel, as being placed in the RAM range, most likely far
from the ROM address, was inflating the XIP images.
Moving the .notes at the end of the read-only section
(consisting of .text, .rodata and unwind info) fixes the problem.
Reported-by: Marc Kleine-Budde <[email protected]>
Signed-off-by: Pawel Moll <[email protected]>
Tested-by: Marc Kleine-Budde <[email protected]>
Signed-off-by: Russell King <[email protected]>
Since commit 1f2bfbd00e "kbuild:
link of vmlinux moved to a script" make clean with M=<dir>
argument (so cleaning external module) removes vmlinux,
System.map and couple of other files from the *main* kernel
build directory! This not what was happening before and almost
certainly not what one would expect.
This patch moves makes the clean target of the script called
only when !KBUILD_EXTMOD.
Signed-off-by: Pawel Moll <[email protected]>
Cc: [email protected] [v3.5+]
Signed-off-by: Michal Marek <[email protected]>
As the current LEDs code breaks other platform, remove it.
It shall be replaced by a generic "MMIO LEDs" driver.
Reported-by: Stephen Warren <[email protected]>
Signed-off-by: Pawel Moll <[email protected]>
Tested-by: Stephen Warren <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
The way the VE motherboard Device Trees were constructed
enforced naming and structure of daughterboard files. This
patch makes it possible to simply include the motherboard
description anywhere in the main Device Tree and retires
the "arm,v2m-timer" alias - any of the motherboard SP804
timers will be used instead.
Signed-off-by: Pawel Moll <[email protected]>
This patch starts using all the configuration infrastructure.
- generic GPIO library is forced now
- sysreg GPIOs are used as MMC CD and WP information sources;
thanks to this MMCI auxiliary data is not longer necessary
- DVI muxer and mode control is removed from non-DT V2P-CA9 code
as this is now handled by the vexpress-dvi driver
- clock generators control is removed as is being handled by the
common clock driver now
- the sysreg and sysctl control is now delegated to the
appropriate drivers and all related code was removed
- NOR Flash set_vpp function has been removed as the control
bit used does _not_ control its VPP line, but the #WP signal
instead (which is de facto unusable in case of Linux MTD
drivers); this also allowed the remove its DT auxiliary
data
The non-DT code defines only minimal required number of
the config devices. Device Trees are updated to make use
of all new features.
Signed-off-by: Pawel Moll <[email protected]>
Add description of all functions provided by Versatile Express
motherboard and daughterboards configuration controllers and
clock dependencies between devices.
Signed-off-by: Pawel Moll <[email protected]>
This is a platform driver for Versatile Express' "system
register" block. It's a random collection of registers providing
the following functionality:
- low level platform functions like board ID access; in order to
use those, the driver must be initialized early, either statically
or based on the DT
- config bus bridge via "system control" interface; as the response
from the controller does not generate interrupt (yet), the status
register is periodically polled using a timer
- pseudo GPIO lines providing MMC card status and Flash WP#
signal control
- LED interface for a set of 8 LEDs on the motherboard, with
"heartbeat", "mmc0" and "cpu0" to "cpu5" as default triggers
Signed-off-by: Pawel Moll <[email protected]>
Versatile Express platform has an elaborated configuration system,
consisting of microcontrollers residing on the mother- and
daughterboards known as Motherboard/Daughterboard Configuration
Controller (MCC and DCC). The controllers are responsible for
the platform initialization (reset generation, flash programming,
FPGA bitfiles loading etc.) but also control clock generators,
voltage regulators, gather environmental data like temperature,
power consumption etc. Even the video output switch (FPGA) is
controlled that way.
Those devices are _not_ visible in the main address space and
the usual communication channel uses some kind of a bridge in
the peripheral block sending commands (requests) to the
controllers and receiving responses. It can take up to
500 microseconds for a transaction to be completed, therefore
it is important to provide a non-blocking interface to it.
This patch adds an abstraction of this infrastructure. Bridge
drivers can register themselves with the framework. Then,
a driver of a device can request an abstract "function" - the
request will be redirected to a bridge referred by thedd
"arm,vexpress,config-bridge" property of the device tree node.
Signed-off-by: Pawel Moll <[email protected]>
This patch adds a DT and non-DT based implementation of
the common clock infrastructure for Versatile Express
platform. It registers (statically or using DT) all
required fixed clocks, initialises motherboard's SP810
cell (that provides clocks for SP804 timers) and
explicitly registers VE "osc" driver, to make the
clock generators available early.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
This driver provides a common clock framework hardware driver
for Versatile Express clock generators (a.k.a "osc") controlled
via the config bus.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
This is a simple driver providing platform restart and power off
functions using VE config infrastructure.
By writing to the "active" attribute of the reboot or reset device,
user can decide what if the platform is supposed to execute full power
cycle (reboot, default) or simply assert system level reset signal.
Signed-off-by: Pawel Moll <[email protected]>
Conflicts:
include/linux/vexpress.h
Base the UART detection heuristic on architecturally defined
MIDR register instead of implementation dependent CBAR. The
only tile using the original memory map is V2P-CA9 with Cortex
A9 r0p1, which MIDR contains value 0x410fc091.
Signed-off-by: Pawel Moll <[email protected]>
hwmon framework driver for Versatile Express sensors, providing
information about board level voltage (only when regulator driver
is not configured), currents, temperature and power/energy usage.
Labels for the values can be defined as DT properties.
Signed-off-by: Pawel Moll <[email protected]>
Acked-by: Guenter Roeck <[email protected]>
Implementation of the regulator framework driver for the
Versatile Express voltage control. Devices without
voltage constraints (ie. "regulator-[min|max]-microvolt"
properties in the DT node) are treated as fixed (or rather
read-only) regulators.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Some regulators can set any voltage within the constraints range,
not being limited to specified operating points.
This patch makes it possible to describe such regulator and makes
the regulator_is_supported_voltage() function behave correctly.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Clocks must be prepared before enabling and unprepared
after disabling. Use appropriate functions to do this
in one go.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Dmitry Torokhov <[email protected]>
Due to automatic merge of a613163dff
"ARM: integrator: convert to common clock" and
56a34b03ff "ARM: versatile: Make
plat-versatile clock optional" two platforms: Integrator and
Versatile Express now select both COMMON_CLK and
PLAT_VERSATILE_CLOCK which breaks building them. Fixed now.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
Versatile Express platform can be used in different configurations,
the console UART used by early printk may be located at different
addresses in the address space.
This patch makes it possible to select the base address of a PL011
UART to be used as a console output in the kernel configuration.
The default behaviour is still the heuristic detecting memory map
on Cortex-A core tiles.
The zImage decompressor will use the same configuration values
or print out nothing if DEBUG_LL is not enabled.
Signed-off-by: Pawel Moll <[email protected]>
This patch adds Device Tree file for the CoreTile Express
A15x2 A7x3 (V2P-CA15_CA7).
Note that the A7 cpu nodes are commented out, as the
big.LITTLE-relevant patches are not upstreamed yet. Till
this time one can use the board with two A15 cores only,
keeping the A7s in reset by adding the following setting
to the board.txt file in Versatile Express configuration
tree:
SCC: 0x018 0x00001FFF
Signed-off-by: Pawel Moll <[email protected]>
SMSC driver requires "vdd33a" and "vddvario" regulator supplies now.
Add fixed regulator describing 3V3 power line (in both motherboard's
Device Trees and the non-DT code) and force fixed regulator config
option if regulators framework is enabled.
Signed-off-by: Pawel Moll <[email protected]>
This patch makes Versatile Express use the common clock framework
instead of the plat-versatile implementation.
It defines clock provider for VE's OSCs (clock generators) and
registers all required fixed and variable clock sources (for both
motherboard and core tile).
This is a simple conversion of the existing state and will be
extended (and migrated to drivers/clk) in the near future.
Signed-off-by: Pawel Moll <[email protected]>
... in preparation for common clock coming for Integrator
and Versatile Express.
Based on Linus Walleij's "ARM: integrator: convert to common
clock" patch.
Signed-off-by: Pawel Moll <[email protected]>
With recent enough motherboard firmware, core tile can be fitted
in either of the two daughterboard sites. The non-DT tile code for
V2P-CA9 did not check that when configuring DVI output nor setting
CLCD pixel clock.
Fixed now, providing "get master site" API in motherboard's code.
Signed-off-by: Pawel Moll <[email protected]>
clk_change_rate() is accessing parent's rate without checking
if the parent exists at all. In case of root clocks this will
cause NULL pointer dereference.
This patch follows what clk_calc_new_rates() does in such
situation.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
Cc: [email protected]
This patch adds an option to instantiate guest virtio-mmio devices
basing on a kernel command line (or module) parameter, for example:
virtio_mmio.devices=0x100@0x100b0000:48
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Rusty Russell <[email protected]>
* Added extra regs for A15 VGIC
* Added A15 architected timer node
* Split A5 and A9 TWD nodes into two separate ones for timer
and watchdog; interrupt definitions fixed on the way
* Fixed typo in A5 GIC compatible value
All the changes courtesy of Marc Zyngier.
Signed-off-by: Pawel Moll <[email protected]>
This patch adds a set of macros that can be used to declare
kernel parameters to be parsed _before_ initcalls at a chosen
level are executed. We rename the now-unused "flags" field of
struct kernel_param as the level. It's signed, for when we
use this for early params as well, in future.
Linker macro collating init calls had to be modified in order
to add additional symbols between levels that are later used
by the init code to split the calls into blocks.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Rusty Russell <[email protected]>
This patch adds Device Tree binding ("arm,versatile-i2c") and
basic support (bus population) to versatile-i2c driver.
Signed-off-by: Pawel Moll <[email protected]>
[wsa: constified match-table]
Signed-off-by: Wolfram Sang <[email protected]>
This patch adds Device Tree file for the CoreTile Express A15x2
(V2P-CA15) with Test Chip 1.
As the chip's GIC has 160 interrupt inputs and equivalent SMM
(FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
increased.
Signed-off-by: Pawel Moll <[email protected]>
This patch adds generic Versatile Express DT machine description,
Device Tree description for the motherboard and documentation for
the bindings.
Signed-off-by: Pawel Moll <[email protected]>
Scan flatten device looking for A5/A9 SCU node and initialize
it using base address in "reg" property. If nothing is found,
assume that there is no special SCU initialization required
and initialize CPUs basing on numbers of "cpu" type devices
in "cpus" node of the Device Tree.
All this happens only if the board was booted with FDT,
otherwise ct_desc callbacks are used.
Signed-off-by: Pawel Moll <[email protected]>
Try to map TWD registers basing on a "arm,*-twd-timer" Device Tree
node. This overrides existing twd_base value.
Signed-off-by: Pawel Moll <[email protected]>
This patch gets rid of the MMIO_P2V and __MMIO_P2V macros,
defining constant virtual base for motherboard and tile
peripherals instead.
Additionally, in preparation for the new motherboard memory
map, the motherboard peripherals are using base pointers
calculated in runtime, instead of compile-time calculated
values.
Signed-off-by: Pawel Moll <[email protected]>
Since commit 576d2f2525 "ARM: add
generic ioremap optimization by reusing static mappings" ioremap()
is trying to reuse existing static mapping when possible.
The condition checking boundaries of the requested and existing
mappings didn't take in-page offset into consideration though,
which lead to obscure and hard to debug problems when requested
mapping crossed end of the static one.
Signed-off-by: Pawel Moll <[email protected]>
Acked-by: Nicolas Pitre <[email protected]>
Signed-off-by: Russell King <[email protected]>
Once the ENDPROC is in place, BSYM() in not longer necessary
to get correct pointer to versatile_secondary_startup().
Tested-by: Jon Medhurst <[email protected]>
Signed-off-by: Pawel Moll <[email protected]>
Acked-by: Dave Martin <[email protected]>
This patch adds processor info for ARM Ltd. Cortex-A7.
A7 is architecturally identical to A15 so it shares the
same SMP initialization code and hwcaps.
Tested-by: Will Deacon <[email protected]>
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Russell King <[email protected]>
This patch, based on virtio PCI driver, adds support for memory
mapped (platform) virtio device. This should allow environments
like qemu to use virtio-based block & network devices even on
platforms without PCI support.
One can define and register a platform device which resources
will describe memory mapped control registers and "mailbox"
interrupt. Such device can be also instantiated using the Device
Tree node with compatible property equal "virtio,mmio".
Cc: Anthony Liguori <[email protected]>
Cc: Michael S.Tsirkin <[email protected]>
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Rusty Russell <[email protected]>
This patch adds missing #includes, makes the driver selectable on
non-PPC OF-enabled platforms and fixes property value accesses to
be correct in Little Endian system.
Cc: Anton Vorontsov <[email protected]>
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Jeff Garzik <[email protected]>
This patch adds processor info for ARM Ltd. Cortex A5,
which has SCU initialisation procedure identical to A9.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
As most of the proc info content is common across all v7
processors, this patch converts existing A9 and generic v7
descriptions into a macro (allowing extra flags in future).
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
The second GIC, present when EB board is used with a MPCore tile,
was initialised starting with irq number 64, which made interrupts
64-95 in the primary GIC unusable.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Russell King <[email protected]>
New IO FPGA implementation for Versatile Express boards contain
MMCI (PL180) cell with FIFO extended to 128 words (512 bytes).
Matt Waddel reports that this patch improves MMC performance on
his vexpress system, and also fixes "mmcblk0: error -5 transferring
data" errors.
Signed-off-by: Pawel Moll <[email protected]>
Tested-by: Matt Waddel <[email protected]>
Signed-off-by: Chris Ball <[email protected]>
If the MMC host controller does not support waiting for card signaling
busy state (MMC_CAP_WAIT_WHILE_BUSY cap), there is no point in prining
the relevant warning message.
Signed-off-by: Pawel Moll <[email protected]>
Reviewed-by: Matt Fleming <[email protected]>
Signed-off-by: Chris Ball <[email protected]>
Commit 18991197b4 added --build-id
linker option when toolchain supports it. ARM one does, but for some
reason places the section at 0 when linker script doesn't mention it
explicitly.
The 1e621a8e37 worked around the problem
removing this section from binary image with explicit objcopy options,
but it still exists in vmlinux, confusing tools like debuggers and perf.
This problem was discussed here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/015994.htmlhttp://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/015994.html
but the proposed changes to the linker script were substantial.
This patch simply places NOTES (36 bytes long, at least when compiled
with CodeSourcery toolchain) between data and bss, which seem to be
the right place (and suggested by the sample linker script in
include/asm-generic/vmlinux.lds.h).
It is enough to place it correctly in vmlinux (so debuggers are happy):
Section Headers:
[11] .data PROGBITS c07ce000 7ce000 020fc0 00 WA 0 0 32
[12] .notes NOTE c07eefc0 7eefc0 000024 00 AX 0 0 4
[13] .bss NOBITS c07ef000 7eefe4 01e628 00 WA 0 0 32
Program Headers:
LOAD 0x008000 0xc0008000 0xc0008000 0x7e6fe4 0x805628 RWE 0x8000
NOTE 0x7eefc0 0xc07eefc0 0xc07eefc0 0x00024 0x00024 R E 0x4
Section to Segment mapping:
Segment Sections...
00 <...> .data .notes .bss
01 .notes
and to get it exposed as /sys/kernel/notes used by perf tools.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Russell King <[email protected]>
Timers on Versatile Express mainboard are used as system clock/event
sources. Driver assumes that they are clocked with 1MHz signal.
Old V2M firmware apparently configured it by default, but on newer
boards one can observe that "sleep 1" command takes over 30 seconds
to finish, as the timers are fed with 32kHz instead...
This patch performs required magic and also removes code clearing
timer's control registers, as exactly the same operations are
performed by the timer driver few jiffies later.
Signed-off-by: Pawel Moll <[email protected]>
Tested-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
This change limits number of GIC-originating interrupts to the
platform maximum (defined by NR_IRQS) while still initialising
all distributor registers.
Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Russell King <[email protected]>
Pawel Moll