The PQFP version have only 3 gpio banks (A, B & C).
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
[[email protected]: correct typo in "status" property]
Signed-off-by: Nicolas Ferre <[email protected]>
pinctrl-names was missing causing mmc pinctrl to never be requested.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Acked-by: Ludovic Desroches <[email protected]>
[[email protected]: added a commit message taken from Ludovic]
Signed-off-by: Nicolas Ferre <[email protected]>
OMAP display subsystem changes for 3.11 (part 2/2)
This is the second part of OMAP DSS changes for 3.11. This part contains the
new DSS device model support.
The current OMAP panel drivers use a custom DSS bus, and there's a hard limit
of one external display block per video pipeline. In the new DSS device model
the devices/drivers are made according to the control bus of the display block,
usually platform, i2c or spi. The display blocks can also be chained so that we
can have separate drivers for setups with both external encoder and panel.
To allow the current board files, which use the old style panels, to function,
the old display drivers are left in their current state, and new ones are added
to drivers/video/omap2/displays-new/. When the board files have been converted
to use the new style panels, we can remove the old code. This is planned to
happen in v3.12.
Having to support two very different DSS device models makes the driver
somewhat confusing in some parts, and prevents us from properly cleaning up
some other parts. These cleanups will be done when the old code is removed.
The new device model is designed with CDF (Common Display Framework) in mind.
While CDF is still under work, the new DSS device model should be much more
similar to CDF's model than the old device model, which should make the
eventual conversion to CDF much easier.
OMAP display subsystem changes for 3.11 (part 1/2)
This is the first part of OMAP DSS changes for 3.11. This part contains fixes,
cleanups and reorganizations that are not directly related to the new DSS
device model that is added in part 2, although many of the reorganizations are
made to make the part 2 possible.
There should not be any functional changes visible to the user except the few
bug fixes.
The main new internal features:
- Display (dis)connect support, which allows us to explicitly (dis)connect a
whole display pipeline
- Panel list, which allows us to operate without the specific DSS bus
- Combine omap_dss_output to omap_dss_device, so that we have one generic
"entity" for display pipeline blocks
Since 4b68520dc0ec96153bc0d87bca5ffba508edfcf
ARM: at91: add AIC5 support
we allocate the at91_extern_irq.
This patch makes it static and stores the non-dt extern irq in the soc
structure. It is then possible to use a at91_get_extern_irq() function
to get the value for outside of the irq driver. It is useful for passing
its value to at91_aic_init().
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Acked-by: Ludovic Desroches <[email protected]>
[[email protected]: rework commit message]
Signed-off-by: Nicolas Ferre <[email protected]>
This board is impossible to found anymore.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
as now we have full DT support of those board
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
the low power version have a mmc-spi
eanble mmc-spi and RV3029C2 RTC in at91_dt_defconfig
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
Merge 9g20 with 9260 and 9g10 with 9261 as those SoCs can run from the same
kernel even in non DT world.
Fix the sam9261ek to allow 9g10 and sam9261 to compile together.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
to prepare the switch to the macro.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
since commit 838a2ae80a
Author: Shawn Guo <[email protected]>
Date: Sat Jan 12 11:50:05 2013 +0000
ARM: use clockevents_config_and_register() where possible
The timer is wrongly configured and result in a nice crash
so revert it on rm9200 timer.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Cc: stable <[email protected]> # 3.8+
Cc: Shawn Guo <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
On the at91_adc a minimal Sample and Hold Time is necessary for the ADC to
guarantee the best converted final value between two channels selection.
This time has to be programmed through the bitfield SHTIM in the
Mode Register ADC_MR.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Ludovic Desroches <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
The sleep mode will allow to put the adc in sleep between conversion.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Ludovic Desroches <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Rename the board-rm9200-dt.c file so that we follow the pattern for
Device Tree board files: board-dt-<name of SoC sharing same core>.c
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
[[email protected]: modify commit message]
Signed-off-by: Nicolas Ferre <[email protected]>
We will produce a board-dt file per SoC core type. That will ease code
readability and will prevent from including superfluous code for supporting
machines that will never be compiled together (particularly the ARM9 and C-A5
upcoming SoCs).
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
[[email protected]: modify commit message]
Signed-off-by: Nicolas Ferre <[email protected]>
This is the legacy platform support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
Make BGA as the default version as we are supposed to just have
to specify when we use the PQFP version.
Issue was existing since commit:
3e90772 (ARM: at91: fix at91rm9200 soc subtype handling).
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Cc: stable <[email protected]> [v3.3]
Signed-off-by: Nicolas Ferre <[email protected]>
/opt/work/linux-2.6/drivers/iio/adc/at91_adc.c: In function 'at91_adc_trigger_handler':
/opt/work/linux-2.6/drivers/iio/adc/at91_adc.c:83:22: error: 'indio_dev' undeclared (first use in this function)
/opt/work/linux-2.6/drivers/iio/adc/at91_adc.c:83:22: note: each undeclared identifier is reported only once for each function it appears in
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Cc: [email protected]
Signed-off-by: Jonathan Cameron <[email protected]>
Use the newly introduce cs-gpios dt support on atmel.
We do not use the hardware cs as it's wired and has bugs and limitations.
As the controller believes that only active-low devices/systems exists.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Grant Likely <[email protected]>
this will allow to detect the link between the switch and the soc
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Cc: [email protected]
Signed-off-by: David S. Miller <[email protected]>
This will allow to use gpio for chip select with no modification in the
driver binding
When use the cs-gpios, the gpio number will be passed via the cs_gpio field
and the number of chip select will automatically increased with max(hw cs, gpio cs).
So if for example the controller has 2 CS lines, and the cs-gpios
property looks like this:
cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
Then it should be configured so that num_chipselect = 4 with the
following mapping:
cs0 : &gpio1 0 0
cs1 : native
cs2 : &gpio1 1 0
cs3 : &gpio1 2 0
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Richard Genoud <[email protected]>
[grant.likely: fixed up type of cs count so min() can do type checking]
Signed-off-by: Grant Likely <[email protected]>
Modify both AT91 and AVR32 platforms.
Use 7 for it as the sam9260 or the sam9g25 have 7 of them DBGU included.
Reported-by: Joachim Eastwood <[email protected]>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
linux,mtd-name allow to specify the mtd name for retro capability with
physmap-flash drivers as boot loader pass the mtd partition via the old
device name physmap-flash.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Do not use the platform_data to pass resource and be smart in the drivers.
Just pass it via resource
Switch to devm_request_and_ioremap at the sametime
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Reviewed-By: Vipin Kumar <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
This is only used by old boards style or via core code.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Cc: Nicolas Ferre <[email protected]>
as this is only used board old style board old mach code
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Cc: Nicolas Ferre <[email protected]>
No one care about them for releases and the machine are present in soc
defconfigs so drop them.
For qil-a9260 and usb-a9260 I maintain them and now switch to the
at91sam9260_defconfig.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Cc: Nicolas Ferre <[email protected]>
If no pinctrl available just report a warning as some architecture may not
need to do anything.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
[[email protected]: adapt the error path, remove unneeded headers]
Signed-off-by: Nicolas Ferre <[email protected]>
Tested-by: Joachim Eastwood <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
/opt/work/linux-2.6/drivers/pinctrl/pinctrl-at91.c: In function 'at91_pinctrl_probe_dt':
/opt/work/linux-2.6/drivers/pinctrl/pinctrl-at91.c:952:12: warning: assignment discards qualifiers from pointer target type
/opt/work/linux-2.6/drivers/pinctrl/pinctrl-at91.c: In function 'at91_gpio_probe':
/opt/work/linux-2.6/drivers/pinctrl/pinctrl-at91.c:1517:17: warning: assignment discards qualifiers from pointer target type
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
If we do this
interrupt-parent = <&pioA>;
interrupts = <7 0x0>;
The current core map the irq correctly but the gpio is not configured as input.
The pinctrl configure the pin as gpio with the correct mux parameter but is
not responsible to configure it as input.
So do it during the xlate
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Set the dbgu pinctrl config by default as we have only one possible config
For other uart set the rxd/txd by default.
For at91sam9x5ek create soc based dts as we need to include specific soc dtsi.
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
This is also include the gpio controller as the IP share both.
Each soc will have to describe the SoC limitation and pin configuration via
DT.
This will allow to do not need to touch the C code when adding new SoC if the
IP version is supported.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
On the at91sam9x5 SoC series, GPIO banks B and D only have 19 and 22
pins. So add a property to set this parameter.
Acked-by: Nicolas Ferre <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Fix also the reg size as we have 512 bytes bank not 256 bytes per gpio/mux
controller
Acked-by: Linus Walleij <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Configure the pin as pio when requested.
It is needed to configure the pin as PIO at "request time" when we are
using DT. Indeed, the muxing via old AT91 API is not allowed anymore if
we are using the plain gpiolib.
Acked-by: Nicolas Ferre <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Instead of check the pointer of the init function, check the new builtin bool
to known if the soc is enabled.
This is needed as with the switch to the pinctrl the init will be NULL on pure
DT SoC.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
without this the gpio will not be muxed as a gpio by the current custom pinmux
or later by the pinctrl
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
