Queues should be empty when released, if not, there is a safety valve.
Make sure the queue is usable after it triggers.
Signed-off-by: Krzysztof Hałasa <[email protected]>
We must not wake the TX queue without free TX descriptors.
sca_xmit() expects at least one free descriptor and BUGs otherwise.
Problem reported and fix tested by Bernie Innocenti and Ward Vandewege.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
This is a driver for SBE Inc.'s dual port T3/E3 WAN cards. Based on
their original GPLed driver.
The original driver tarball is now accessible at
http://userweb.kernel.org/~chris/SBE_2T3_Linux_2.0c.tgz
It needs at least a new generic HDLC setup code (not yet written) before
moving to drivers/net/wan.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
SBE 2T3E3 cards use DECchips 21143 but they need a different driver.
Don't even try to use a normal tulip driver with them.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Alan <[email protected]> writes:
> program: /home/alan/GitTrees/linux-2.6-mid-ref/scripts/mod/modpost -o
> Module.symvers -S vmlinux.o
>
> Program received signal SIGSEGV, Segmentation fault.
It just hit me.
It's the offset calculation in reloc_location() which overflows:
return (void *)elf->hdr + sechdrs[section].sh_offset +
(r->r_offset - sechdrs[section].sh_addr);
E.g. for the first rodata r entry:
r->r_offset < sechdrs[section].sh_addr
and the expression in the parenthesis produces 0xFFFFFFE0 or something
equally wise.
Reported-by: Alan <[email protected]>
Signed-off-by: Krzysztof Hałasa <[email protected]>
Tested-by: Alan <[email protected]>
Signed-off-by: Michal Marek <[email protected]>
Fixes the following on IXP425 little-endian:
NPE-C: firmware functionality 0x5, revision 0x2:1
alg: skcipher: Test 1 failed on encryption for ecb(des)-ixp4xx
00000000: 01 23 45 67 89 ab cd e7
alg: skcipher: Test 1 failed on encryption for ecb(des3_ede)-ixp4xx
00000000: 73 6f 6d 65 64 61 74 61
alg: skcipher: Test 1 failed on encryption for ecb(aes)-ixp4xx
00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff
Signed-off-by: Krzysztof Hałasa <[email protected]>
Acked-by: Christian Hohnstaedt <[email protected]>
With port configured with PCR_FRM_SYNC_OUTPUT* and external clock, bringing
the hdlcX interface up and down without active clock supplied to the HSS
causes a TX lockup. We don't support channelized/partial interfaces so
FRaMe signals can't be used anyway, disabling them makes the lockup go away.
Changes to this logic will be required if we want to support channelized
HSS mode (this is most probably bug in NPE-A HSS firmware).
Signed-off-by: Krzysztof Hałasa <[email protected]>
This doesn't change the clock limits (minimums), i.e. it won't make it
output 720x576 PAL nor 720x480 NTSC, but it will work with modes like
1080i etc. (including GLX and textured Xvideo, not sure about the
overlay).
Tested on i915 + analog VGA, it would be worth checking if newer chips
(and which ones) still support interlaced mode.
Signed-off-by: Krzysztof Halasa <[email protected]>
Signed-off-by: Eric Anholt <[email protected]>
tx_queue is used as a temporary queue when not allowed to queue skb
directly to the hw device driver (which may sleep). Most paths flush
it before returning, but ppp_start() currently cannot. Make sure we
don't leave skbs pointing to a non-existent device.
Thanks to Michael Barkowski for reporting this problem.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
PrPMC1100 is handled by IXDP425 platform code, there is no need for
duplicate set of macros. Remove them.
Signed-off-by: Krzysztof Hałasa <[email protected]>
IXP4xx CPUs can indirectly access the whole 4 GB PCI MMIO address space (using
the non-prefetch registers). Previously the available space depended on the CPU
variant, since one of the IXP43x platforms needed more than the usual 128 MB.
1 GB should be enough for everyone, and if not, we can trivially increase it.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Instead of including the heavy linux/mm.h for VMALLOC_START, test the addresses
against PCI MIN and MAX addresses. Indirect PCI uses 1:1 mapping for MMIO space
making this change possible.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Clock generators used by IXP4xx processors are usually 33.333 MHz, sometimes
33.33 MHz and few platforms use 33 MHz. The timers tick twice as fast,
that means 66.666, 66.66 or 66 MHz. Current 66.666666 MHz means 10 ppm
offset from the usual 66.666 MHz.
Signed-off-by: Krzysztof Hałasa <[email protected]>
IXDP425 and Coyote aren't based on IXP2000 but on IXP425.
Signed-off-by: Krzysztof Halasa <[email protected]>
Signed-off-by: Jiri Kosina <[email protected]>
Cisco HDLC uses keepalive packets and sequence numbers to determine link
state. In rare cases both ends could transmit keepalive packets at the same
time, causing the received sequence numbers to be treated as incorrect.
Now we accept our current sequence number as well as the previous one.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
HSS usually uses external clocks, so it's not a big deal. Internal clock
is used for direct DTE-DTE connections and when the DCE doesn't provide
it's own clock.
This also depends on the oscillator frequency. Intel seems to have
calculated the clock register settings for 33.33 MHz (66.66 MHz timer
base). Their settings seem quite suboptimal both in terms of average
frequency (60 ppm is unacceptable for G.703 applications, their primary
intended usage(?)) and jitter.
Many (most?) platforms use a 33.333 MHz oscillator, a 10 ppm difference
from Intel's base.
Instead of creating static tables, I've created a procedure to program
the HSS clock register. The register consists of 3 parts (A, B, C).
The average frequency (= bit rate) is:
66.66x MHz / (A + (B + 1) / (C + 1))
The procedure aims at the closest average frequency, possibly at the
cost of increased jitter. Nobody would be able to directly drive an
unbufferred transmitter with a HSS anyway, and the frequency error is
what it really counts.
I've verified the above with an oscilloscope on IXP425. It seems IXP46x
and possibly IXP43x use a bit different clock generation algorithm - it
looks like the avg frequency is:
(on IXP465) 66.66x MHz / (A + B / (C + 1)).
Also they use much greater precomputed A and B - on IXP425 it would
simply result in more jitter, but I don't know how does it work on
IXP46x (perhaps 3 least significant bits aren't used?).
Anyway it looks that they were aiming for exactly +60 ppm or -60 ppm,
while <1 ppm is typically possible (with a synchronized clock, of
course).
The attached patch makes it possible to set almost any bit rate
(my IXP425 533 MHz quits at > 22 Mb/s if a single port is used, and the
minimum is ca. 65 Kb/s).
This is independent of MVIP (multi-E1/T1 on one HSS) mode.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
PCI200SYN has its own PCI subsystem device ID for 3+ years, now it's
time to remove the generic PLX905[02] ID from the driver. Anyone with
old EEPROM data will have to run the upgrade.
Having the generic PLX905[02] (PCI-local bus bridge) ID is harmful
as the driver tries to handle other devices based on these bridges.
Signed-off-by: Krzysztof Halasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
E100 places it's RX packet descriptors inside skb->data and uses them
with bidirectional streaming DMA mapping. Data in descriptors is
accessed simultaneously by the chip (writing status and size when
a packet is received) and CPU (reading to check if the packet was
received). This isn't a valid usage of PCI DMA API, which requires use
of the coherent (consistent) memory for such purpose. Unfortunately e100
chips working in "simplified" RX mode have to store received data
directly after the descriptor. Fixing the driver to conform to the API
would require using unsupported "flexible" RX mode or receiving data
into a coherent memory and using CPU to copy it to network buffers.
This patch, while not yet making the driver conform to the PCI DMA API,
allows it to work correctly on X86 with swiotlb (while not breaking
other architectures).
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
E100 places it's RX packet descriptors inside skb->data and uses them
with bidirectional streaming DMA mapping. Unfortunately it fails to
transfer skb->data ownership to the device after it reads the
descriptor's status, breaking on non-coherent (e.g., ARM) platforms.
This have to be converted to use coherent memory for the descriptors.
Signed-off-by: Krzysztof Halasa <[email protected]>
Acked-by: Jeff Kirsher <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Adds USB ID for Turtelizer, an FT2232L-based JTAG/RS-232 adapter.
Signed-off-by: Krzysztof Ha³asa <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
With no IRQ available/defined, RTC-CMOS driver prints something like:
rtc0: alarms up to one no, y3k, 114 bytes nvram
^^^^
I guess the following is a bit easier to understand:
rtc0: no alarms, y3k, 114 bytes nvram
Signed-off-by: Krzysztof Halasa <[email protected]>
Cc: David Brownell <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Map unused registers at the end of DMA region at 64 MB to allow PCI masters
to cross the boundary when prefetching data from SDRAM.
Signed-off-by: Krzysztof Hałasa <[email protected]>
There is another user of IXP4xx queue manager, fix it.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
The userspace interfaces are protected by CONFIG_* ifdefs
and that of course can't work.
Reported by Jaswinder Singh Rajput.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Also remove unneeded last_rx update from Synclink drivers.
Synclink part mostly by Stephen Hemminger.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Use the internal get_stats() by default.
Fixes LMC and wanXL drivers.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
The PHYLIB mdio code has more problems in error paths:
- mdiobus_release can be called before bus->state is set to
MDIOBUS_REGISTERED
- mdiobus_scan allocates resources which need to be freed
- the comment is wrong, the resistors used are actually pull-ups.
Signed-off-by: Krzysztof Halasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
kernel BUG at drivers/net/phy/mdio_bus.c:165!
Unable to handle kernel NULL pointer dereference at virtual address 00000000
How?
mdiobus_alloc() sets bus->state = MDIOBUS_ALLOCATED.
mdiobus_register() sets bus->state = MDIOBUS_REGISTERED but then can
fail (mdiobus_scan()) returning an error to the caller.
The caller aborts correctly with mdiobus_free() which does:
if (bus->state == MDIOBUS_ALLOCATED) {
kfree(bus);
return;
}
BUG_ON(bus->state != MDIOBUS_UNREGISTERED);
Signed-off-by: Krzysztof Halasa <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Supporting both original SCA and SCA-II in one file was nice at some
point but now it's increasingly painful.
Signed-off-by: Krzysztof Hałasa <[email protected]>
Krzysztof Hałasa