4 Commits
Author SHA1 Message Date
H. J. Lu 9c184a073b [IA64] Fix 2.6 kernel for the new ia64 assembler
The new ia64 assembler uses slot 1 for the offset of a long (2-slot)
instruction and the old assembler uses slot 2. The 2.6 kernel assumes
slot 2 and won't boot when the new assembler is used:

http://sources.redhat.com/bugzilla/show_bug.cgi?id=1433

This patch will work with either slot 1 or 2.

Patch provided by H.J. Lu

Signed-off-by: Tony Luck <[email protected]>
2005-10-25 15:05:45 -07:00
H. J. Lu 36d57ac4a8 [PATCH] auxiliary vector cleanups
The size of auxiliary vector is fixed at 42 in linux/sched.h.  But it isn't
very obvious when looking at linux/elf.h.  This patch adds AT_VECTOR_SIZE
so that we can change it if necessary when a new vector is added.

Because of include file ordering problems, doing this necessitated the
extraction of the AT_* symbols into a standalone header file.

Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
2005-09-07 16:57:21 -07:00
H. J. Lu 763b3917e7 [IA64] Fix a typo in arch/ia64/kernel/entry.S
Both 2.4 and 2.6 kernels need this patch for the next binutils.

Signed-off-by: Tony Luck <[email protected]>
2005-07-08 13:23:49 -07:00
H. J. Lu fd51f666fa [PATCH] i386/x86_64 segment register access update
The new i386/x86_64 assemblers no longer accept instructions for moving
between a segment register and a 32bit memory location, i.e.,

        movl (%eax),%ds
        movl %ds,(%eax)

To generate instructions for moving between a segment register and a
16bit memory location without the 16bit operand size prefix, 0x66,

        mov (%eax),%ds
        mov %ds,(%eax)

should be used. It will work with both new and old assemblers. The
assembler starting from 2.16.90.0.1 will also support

        movw (%eax),%ds
        movw %ds,(%eax)

without the 0x66 prefix. I am enclosing patches for 2.4 and 2.6 kernels
here. The resulting kernel binaries should be unchanged as before, with
old and new assemblers, if gcc never generates memory access for

               unsigned gsindex;
               asm volatile("movl %%gs,%0" : "=g" (gsindex));

If gcc does generate memory access for the code above, the upper bits
in gsindex are undefined and the new assembler doesn't allow it.

Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
2005-05-01 08:58:48 -07:00