This header was being rewritten while the asm-generic kbuild support
was in flight, so it missed out on the update. Punt the stub and use
the kbuild now that everything has settled.
Signed-off-by: Mike Frysinger <[email protected]>
Now that common code supports SMP systems, switch our SMP atomic logic
over to it to avoid code duplication.
Signed-off-by: Mike Frysinger <[email protected]>
Only a few core funcs need to be implemented for SMP systems, so allow the
arches to override them while getting the rest for free.
At least, this is enough to allow the Blackfin SMP port to use things.
Signed-off-by: Mike Frysinger <[email protected]>
Cc: Arun Sharma <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Since arches are expected to implement this guy, add a common version for
people the same way as atomic_clear_mask is handled.
Signed-off-by: Mike Frysinger <[email protected]>
Cc: Arun Sharma <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
The atomic helpers are supposed to take an atomic_t pointer, not a random
unsigned long pointer. So convert atomic_clear_mask over.
While we're here, also add some nice documentation to the func.
Signed-off-by: Mike Frysinger <[email protected]>
Cc: Arun Sharma <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
We already declared inc/dec helpers, so we don't need to call the
atomic_{add,sub}_return funcs directly.
Signed-off-by: Mike Frysinger <[email protected]>
Cc: Arun Sharma <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
This header isn't exported to user-space, and even if it was, the
__KERNEL__ check covers the entire file, so we'd get a useless stub in the
first place. So punt it.
Signed-off-by: Mike Frysinger <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
The bug in the BF526 rom when doing a software reset exists only in older
silicon versions, so don't clear SWRST on newer parts.
Signed-off-by: Mike Frysinger <[email protected]>
The BF51x's alternative portmux Kconfig options were copy & pasted from
the BF52x, but never tweaked to reflect it. So drop the old options as
they were never used (and were simply wrong), and add the BF51x specific
pieces to the Kconfig and header.
Signed-off-by: Mike Frysinger <[email protected]>
Back in commit c03c2a8734, we fixed logic in the non-bf54x
GPIO resume code to set the data levels properly before the direction
to avoid spurious line glitches. But we missed the bf54x code paths.
So add the same fix there.
Signed-off-by: Mike Frysinger <[email protected]>
No need to reload these registers constantly since they're always
available (we're not making any function calls in between).
Signed-off-by: Mike Frysinger <[email protected]>
The Blackfin C ABI says we do not need to save/restore R0-R3 and P0-P2
as they are available as scratch registers. So don't bother.
Signed-off-by: Mike Frysinger <[email protected]>
Re-architect how we save/restore the gpio/port logic that only pertains
to bf538/bf539 parts by pulling it out of the core code paths and pushing
it out to bf538-specific locations.
Signed-off-by: Mike Frysinger <[email protected]>
The current save logic used in hibernation is to do a MMR load (base +
offset) into a register, and then push that onto the stack. Then when
restoring, pop off the stack into a register followed by a MMR store
(base + offset). These use plenty of 32bit insns rather than 16bit,
are pretty long winded, and full of pipeline bubbles.
So, by taking advantage of MMRs that are contiguous, the multi-register
push/pop insn, and register abuse, we can shrink this code considerably.
When saving, the new logic does a lot of loads into the data and pointer
registers before executing a single multi-register push insn. Then when
restoring, we do a single multi-register pop insn followed by a lot of
stores. Overall, this allows us to cut the insn count by ~30%, the code
size by ~45%, and drastically reduce the register hazards that trigger
bubbles in the pipeline.
Signed-off-by: Mike Frysinger <[email protected]>
EVT0 is for emulation, EVT1 is for reset, and EVT4 is the "global int
disable" region. None of these are used by software (or even hardware),
so don't bother saving/restoring them when we hibernate since nothing
ever uses these in Linux (the only thing they would be useful for is
core-memory scratch, but that's just crazy talk).
Signed-off-by: Mike Frysinger <[email protected]>
This defines only get used in the hibernate code, so remove them from the
global dpmc header as no one else cares.
Signed-off-by: Mike Frysinger <[email protected]>
The RETE/RETN registers are only used in emulation(JTAG) and NMI nodes,
or as scratch registers, neither of which need to be saved/restored as
this code doesn't execute at those core event levels.
Signed-off-by: Mike Frysinger <[email protected]>
For parts with more than one SIC_IWR, we can optimize the writing
a little bit using better Blackfin insns.
Signed-off-by: Mike Frysinger <[email protected]>
Have the logic that uses peripheral interrupt blocks key off of pint
defines rather than CPU names so that things are generalized across
families.
Signed-off-by: Mike Frysinger <[email protected]>
Have the code work off of MMR names rather than CPU defines so there is
less code to tweak in the future with new parts.
Signed-off-by: Mike Frysinger <[email protected]>
These defines don't accomplish much as GPIO_# is the same thing as #.
Each CPU already provides helpful symbolic defines like GPIO_<PIN>
which everyone uses, so just punt these # ones.
Signed-off-by: Mike Frysinger <[email protected]>
Not sure how these guys slipped in, but they're annoying me.
So bring these unicode space gremlins down to earth to normal
ascii spaces.
Signed-off-by: Mike Frysinger <[email protected]>
For now, this only supports gptimers. Support for dedicated PWM devices
as found on newer parts to come.
Signed-off-by: Michael Hennerich <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
The API is geared around timer ids, except for the act of enabling
and disabling timers. So add a small helper to fill out the gap.
Signed-off-by: Mike Frysinger <[email protected]>
Now that asm/gptimers.h has the hardware register struct layout, there's
no need to duplicate things locally.
Signed-off-by: Mike Frysinger <[email protected]>
Passing a non-simple expression in as the addr arg could incorrectly
apply the pointer cast resulting in misbehavior. Add proper paren.
Signed-off-by: Mike Frysinger <[email protected]>
The documentation for the IMDMA channels appears to be incorrect.
These DMA blocks don't actually have PERIPHERAL_MAP MMRs for us
to access. Attempts to do so lead to system mmr hardware errors.
Signed-off-by: Mike Frysinger <[email protected]>
The Blackfin mutex.h is merely a copy of an older asm-generic/mutex-dec.h,
so punt it and just use the common one directly.
Signed-off-by: Mike Frysinger <[email protected]>
This moves the double fault data used at boot time into a single struct
which can then easily be addressed with indexed loads rather than having
to explicitly load multiple addresses.
Signed-off-by: Mike Frysinger <[email protected]>
The default for the Blackfin SPI driver is 8 bits and dma disabled,
so many of the bfin5xx_spi_chip resources are redundant. So punt
those parts.
Further, drivers should themselves be declaring 16 bit transfers,
so for those that do, and for the ones which no longer do 16 bit
transfers, drop the bfin5xx_spi_chip resources.
Signed-off-by: Mike Frysinger <[email protected]>
This doesn't cause any real bugs, but it should still be fixed.
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
The "channel_program" member was renamed to "adjust_channel_params",
but the documentation wasn't updated.
Reported-by: Sergei Shtylyov <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
We want people to just use the list now rather than hitting up people
who are no longer responsible for it.
Signed-off-by: Mike Frysinger <[email protected]>
Acked-by: Michael Hennerich <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Since we have a struct that defines the sizes of the registers, we don't
need to explicitly use the 16bit read/write helpers. Let the code figure
out which size access to make based on the size of the C type.
There should be no functional changes here.
Signed-off-by: Mike Frysinger <[email protected]>
Acked-by: Wolfgang Grandegger <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
If we look closely, the 4 writes to TRANSMIT_CHL.id1 can be collapsed
down into much simpler code. So do just that.
This also fixes a build failure due to the I/O macros no longer
getting pulled in. Their minor (and accidental) usage here gets
dropped as part of the unification.
Signed-off-by: Mike Frysinger <[email protected]>
Acked-by: Wolfgang Grandegger <[email protected]>
Acked-by: Kurt Van Dijck <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
The socketcan-core lists require subscription, so mark them as such.
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
There's no need for these queue funcs to be inlined, so drop the
markings. This shaves off a few hundred duplicated bytes.
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Grant Likely <[email protected]>
Rather than hardcoding the register sizes/offsets in this file, use the
existing struct in the spi header for reading/writing the hardware.
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Grant Likely <[email protected]>
The default bits per word setting should be 8 bits, but since most of our
devices have been explicitly setting this up, we didn't notice when the
default stopped working.
At the moment, any default transfers without an explicit bit size setting
error out with:
bfin-spi bfin-spi.0: transfer: unsupported bits_per_word
So in the transfer logic, have a bits_per_word setting of 0 fall into the
8 bit transfer logic.
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Grant Likely <[email protected]>
This board has hardware switches for selecting SPI or I2C, so don't
require I2C for this driver.
Signed-off-by: Mike Frysinger <[email protected]>
Acked-by: Liam Girdwood <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
The codec name should not have a "-codec" suffix since this is not part of
a MFD. This was incorrectly changed during the multi-component updated.
Signed-off-by: Mike Frysinger <[email protected]>
Acked-by: Liam Girdwood <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
The only thing the init func does is register a spi driver, so if that
fails, we return the value back up to the caller who will display an
error message for us. So drop the redundant checking/message.
Signed-off-by: Mike Frysinger <[email protected]>
Acked-by: Liam Girdwood <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
After the prefetch/list.h restructure, drivers need to explicitly include
linux/prefetch.h in order to use the prefetch() function. Otherwise, the
current driver fails to build:
drivers/usb/musb/musb_core.c: In function 'musb_write_fifo':
drivers/usb/musb/musb_core.c:219: error: implicit declaration of function 'prefetch'
make[3]: *** [drivers/usb/musb/musb_core.o] Error 1
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
The new instruction_pointer_set helper is defined for people who have
converted to asm-generic/ptrace.h, so don't use it generally unless
the arch needs it (in which case it has been converted). This should
fix building of kgdb tests for arches not yet converted.
Signed-off-by: Mike Frysinger <[email protected]>
Acked-by: Stephen Rothwell <[email protected]>
Cc: Jason Wessel <[email protected]>
Cc: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
The documentation is a little iffy as to whether these are actual MMRs,
but reading them on the hardware works, and the previous version of this
logic (the SDH) had PID[4567]. So add it for RSI too.
Signed-off-by: Mike Frysinger <[email protected]>
Looks like the copying of MMR defines from the SDH block missed updating
the addresses of the RSI_PID# registers. So tweak them to reflect the
actual hardware.
Signed-off-by: Mike Frysinger <[email protected]>
The bf52x/bf54x have the incorrect addresses for USB_EP_NI7_RXINTERVAL
and USB_EP_NI7_TXCOUNT, so adjust those.
Further, the bf54x header puts the USB defines in the wrong place, so
shuffle them back to the right grouping.
Signed-off-by: Mike Frysinger <[email protected]>
This code was mostly developed against a BF54x, so some BF537-specific
issues were missed.
The PPI block starts at PPI_CONTROL, not PPI_STATUS (which is the reverse
of the EPPI block).
The MDMA block starts at MDMA_NEXT_DESC_PTR, not MDMA_CONFIG. Seems the
sim does not catch misreads here so that'll need to get fixed.
The gptimer block is mostly 32bit regs, not 16bit. Use the gptimer struct
to figure that out rather than hardcoding it locally.
Signed-off-by: Mike Frysinger <[email protected]>
Now that the serial code has been unified in bfin_serial.h, and the
Blackfin UART driver pushed its resources to the boards files, we
don't need these headers anymore.
Signed-off-by: Mike Frysinger <[email protected]>
Any consumer that needs to access the MMRs has to provide these helpers,
so make the default into useless stubs.
Signed-off-by: Mike Frysinger <[email protected]>
The Blackfin arch, like the x86 arch, needs to adjust the PC manually
after a breakpoint is hit as normally this is handled by the remote gdb.
However, rather than starting another arch ifdef mess, create a common
GDB_ADJUSTS_BREAK_OFFSET define for any arch to opt-in via their kgdb.h.
Signed-off-by: Mike Frysinger <[email protected]>
Cc: Oleg Nesterov <[email protected]>
Cc: Jason Wessel <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: "H. Peter Anvin" <[email protected]>
Acked-by: Paul Mundt <[email protected]>
Acked-by: Dongdong Deng <[email protected]>
Cc: Sergei Shtylyov <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
This is a series of low level ptrace unification steps to make it easier
for common code (like KGDB) to poke at register state. This also avoids
having to duplicate higher level operations for most ports which don't
have special needs for accessing things.
This patch:
This implements a bunch of helper funcs for poking the registers of a
ptrace structure. Now common code should be able to portably update
specific registers (like kgdb updating the PC).
Signed-off-by: Mike Frysinger <[email protected]>
Cc: Oleg Nesterov <[email protected]>
Cc: Jason Wessel <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: "H. Peter Anvin" <[email protected]>
Cc: Paul Mundt <[email protected]>
Cc: Sergei Shtylyov <[email protected]>
Cc: Dongdong Deng <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
The copy_to_user_page() function is supposed to flush the icache on the
memory that was written, but the current asm-generic version lacks that
logic. While normally it isn't a big deal as the asm-generic version of
icache flushing is a stub, it is a deal for ports that want to use the
asm-generic version as a baseline and then overlay its own specific parts
(like icache flushing).
Signed-off-by: Mike Frysinger <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
The Blackfin percpu input sections are outdated, so rather than update
them, drop them completely and use the new common define.
Signed-off-by: Mike Frysinger <[email protected]>
Since the bfin_write() func needs proper type information in order to
expand into the right bfin_writeX() variant, preserve the addr's type
when setting up the local __addr. Otherwise the helpers will detect
the variant based upon sizeof(void) which is almost never right.
Signed-off-by: Mike Frysinger <[email protected]>
Both the BF548-EZKIT and the BF561-EZKIT use top boot flashes, so now
that Das U-Boot uses the last small sector for its environment, update
their nor layout in the kernel accordingly.
Signed-off-by: Mike Frysinger <[email protected]>
Turns out the documentation is wrong and doing "RAISE 1" does not result
in a software reset, only a core reset. So when the on-chip rom has a
functioning reset helper, use it.
Signed-off-by: Mike Frysinger <[email protected]>
These boards don't have AD1980 modules, and that device is deprecated,
so don't bother building it up by default anymore.
Signed-off-by: Mike Frysinger <[email protected]>
Since the value of these MMRs aren't changing, store the value in a local
variable and work off of that. This avoids multiple MMR reads which are
implicitly forced by the volatile markings.
Signed-off-by: Mike Frysinger <[email protected]>
The BF537 SIC combines the gpio port H mask A interrupts with the
emac rx interrupt, so we need to demux this in software.
It also combines the gpio port H mask B and the emac tx interrupts,
and the watchdog and port F mask B interrupts, but since we don't
support mask B yet, just add the defines for now.
Signed-off-by: Mike Frysinger <[email protected]>
The search logic in the gpio demux walks all possible gpio blocks starting
at the specified pin. The trouble on bf537 parts when we demux the port
F and port G mask A interrupts is that we also demux port H mask A ints.
Most of the time this isn't an issue as people don't usually use port H,
but might as well avoid it when possible.
Signed-off-by: Mike Frysinger <[email protected]>
This functionality was merged into the common bfin_pm_standby_ctrl func
some time ago, so punt these now unused funcs and data, and localize the
wake funcs that aren't needed externally anymore.
Signed-off-by: Mike Frysinger <[email protected]>
The SIC interrupt line muxing that the bf537 does is specific to this
CPU (thankfully), so rip it out of the common code and move it to a
bf537-specific file. This tidies up the common code significantly.
Signed-off-by: Mike Frysinger <[email protected]>
These are only used in a few internal Blackfin places, so move the irq
prototypes out of the global header and into the internal irq one. No
functional changes other than shuffling locales.
Signed-off-by: Mike Frysinger <[email protected]>
Prefer MMR named checks over part-specific lists, condense duplicated
code across different #ifdef branches, simplify CONFIG_PM ifdefs, and
drop unused kgdb header.
Signed-off-by: Mike Frysinger <[email protected]>
After some cache setup reordering changesets, the blackfin_cpudata init
was left behind. While cpu0's data was correct, cpu1's data was not.
Not that big of a deal as these are only used in the cpuinfo output, but
should still be fixed. So move the setup of these fields to the common
cache setup function to avoid this happening again in the future.
Signed-off-by: Mike Frysinger <[email protected]>
The smp flush lines are too long and have too many newlines, so scale
them back to match the other lines.
The %p modifier shows "(null)" for 0, so use %08x instead.
Signed-off-by: Mike Frysinger <[email protected]>
Mike Frysinger