They aren't going anywhere, and probing on DDC can cause the panel to
blank briefly, so read them up front and cache them for later queries.
v2: fix potential NULL derefs in intel_dp_get_edid_modes and
intel_dp_get_edid (Jani)
copy full EDID length, including extension blocks (Takashi)
free EDID on teardown (Takashi)
v3: malloc a new EDID buffer that's big enough for the memcpy (Chris)
v4: change handling of NULL EDIDs, just preserve the NULL behavior
across detects and mode list fetches rather than trying to re-fetch
the EDID (Chris)
v5: be glad that Chris is around to remind me to hit C-x C-s before
committing.
References: https://bugs.freedesktop.org/show_bug.cgi?id=46856
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
This prevents the HDMI detect functions from poking at an eDP
connected panel, which can lead to trouble.
[danvet: Note that we have some other reports of DP vs. HDMI fighting,
but the general case is a much bigger fish to fry.]
References: https://bugs.freedesktop.org/show_bug.cgi?id=42278
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Media turbo requests can either use RPVSWREQ or RPNSWREQ to indicate
what the interrupt handler should do. Since we only deal with the
latter in our turbo code, make the media engine use that for turbo
requests.
Cc: [email protected].
Tested-by: Joe Bloggsian <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Eugeni Dodonov <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
PCH PLLs aren't required for outputs on the CPU, so we shouldn't just
treat them as part of the pipe.
So split the code out and manage PCH PLLs separately, allocating them
when needed or trying to re-use existing PCH PLL setups when the timings
match.
v2: add num_pch_pll field to dev_priv (Daniel)
don't NULL the pch_pll pointer in disable or DPMS will fail (Jesse)
put register offsets in pll struct (Chris)
v3: Decouple enable/disable of PLLs from get/put.
v4: Track temporary PLL disabling during modeset
v5: Tidy PLL initialisation by only checking for num_pch_pll == 0 (Eugeni)
v6: Avoid mishandling allocation failure by embedding the small array of
PLLs into the device struct
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44309
Signed-off-by: Jesse Barnes <[email protected]> (up to v2)
Signed-off-by: Chris Wilson <[email protected]> (v3+)
Reviewed-by: Eugeni Dodonov <[email protected]>
Tested-by: Jesse Barnes <[email protected]>
Reviewed-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
When the PCH split occurred, hw dropped support for separate hsync and
vsync disable in the VGA DAC. So add a PCH specific DPMS function that
just uses the port enable bit for controlling DPMS states.
Before this fix, when anything other than a full DPMS off occurred,
the VGA port would be left enabled and scanning out while all the other
heads would turn off as expected.
v2: duplicate encoder helper vtable into pch and gmch versions (Daniel)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48491
Reviewed-by: Chris Wilson <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
[danvet: s/intel_crt_dpms/gmch_crt_dpms as suggested by Chris.]
Signed-off-by: Daniel Vetter <[email protected]>
On IVB, there are two sets of panel backlight regs: one in the CPU and
one in the PCH. The CPU ones aren't generally used, so on IVB make sure
we allow the PCH regs to actually control the backlight.
v2: remove unused pwm variable (Daniel)
move to init_hw function so we override on resume too
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
We'll probably need new init functions and will need to test it.
v2: fix impossible GEN6 && GEN7 condition, move to Daniel's new init function
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Both PCH and CPU eDP are DP, so set the is_dp flag to true. Add
is_cpu_edp and is_pch_edp bools to make checking for each less verbose
(rather than has_edp_encoder && !intel_encoder_is_pch_edp() sprinkled
everywhere). And rename the "has_edp_encoder" variable to just
"edp_encoder".
With the above variables cleaned up, the rest of the code becomes a bit
more readable and clear.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Chris Wilson <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
ValleyView has a new interrupt architecture; best to put it in a new set
of functions. Also make sure the ring mask functions handle ValleyView.
FIXME: fix flipping; need to enable interrupts and call prepare/finish
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
ValleyView handles force wake differently than previous chipsets, so add
a couple of new functions for it. But leave it disabled by default
until we test it (need a chip with the Punit enabled first).
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
... and bind it right to the PCI id.
Note that there are still a few things to fix here:
- we need to move the tlb flush to a better place in drm/i915.
- we need to check snoop support on vlv and implement it.
Signed-off-by: Jesse Barnes <[email protected]>
[danvet: squash follow-on patch and add todo items to commit msg.]
Signed-off-by: Daniel Vetter <[email protected]>
We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
register for doing so is above the range we normally map. Map the whole
register space to make sure we can get it.
v2: only map the larger space on gen7+ (Daniel)
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Set required clock gating and chicken bits on VLV.
v2: set PIXEL_SUBSPAN_COLLECT_OPT_DISABLE too (Ben)
move function below ivb version to pretend to be consistent (Ben)
Reviewed-by: Ben Widawsky <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
ValleyView puts some display related registers like the PLL controls and
dividers behind the DPIO bus. Add simple indirect register access
routines to get to those registers.
v2: move new wait_for macro to intel_drv.h (Ben)
fix DPIO_PKT double write (Ben)
add debugfs file
Reviewed-by: Ben Widawsky <[email protected]>
Reviewed-by: Eugeni Dodonov <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Add support for ValleyView watermark handling.
v2: remove unused reg & bit definitions (Ben)
Acked-by: Ben Widawsky <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
For use by the rest of the ValleyView code.
v2: fix desktop variant to not set is_mobile (Ben)
Acked-by: Ben Widawsky <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
They were all over the place, order them by position and add a few.
v2: add gen indications to the new bits (Ben)
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Ben Widawsky <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
It's only used by the main read/write functions, so we can keep it with
them.
Signed-off-by: Jesse Barnes <[email protected]>
Acked-by: Ben Widawsky <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Though we may as well just merge this entry with the main PCI one at
this point. Unless Alex returns one day at least...
Signed-off-by: Jesse Barnes <[email protected]>
I find I have less and less time to manage PCI patches and so I've been
looking for a replacement. Bjorn has been substitute maintainer several
times, and acts as de-facto maintainer for certain portions anyway.
He's kindly agreed to take over in my stead; this makes it official.
Acked-by: Bjorn Helgaas <[email protected]>
Signed-off-by: Jesse Barnes <[email protected].
intel_framebuffer_init does some basic sanity checking of the pixel format,
but is used by the plane code in addition to the primary crtc. So it
needs to contain any formats used in either place.
Add the XBGR8888 format to the checklist so the plane code can use it.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
They're not really errors (well actually I don't know; I don't
understand _DSM and _MUX well enough to say, but I do know they spam
people's logs and seem to be harmless).
Signed-off-by: Jesse Barnes <[email protected]>
[danvet: The _DSM error got remove in another patch already]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44250
Signed-off-by: Daniel Vetter <[email protected]>
Now that we're using the sprite WM fields, we need to take care not to
clobber them in the main update_wm functions. While we're at it, make
sure we mask out the old sprite wm value before or'ing in the new one
when the sprite wm is updated.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
This cleans up the mode set path a little further, making it easier to
extend for future platforms.
Signed-off-by: Jesse Barnes <[email protected]>
[danvet: shut up stupid gcc warning about potential use of
un-initlized fp2]
Signed-off-by: Daniel Vetter <[email protected]>
Makes the mode set routine a little cleaner and easier to extend.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
We can call the plane init function unconditionally, but don't need to
complain if it fails, since that will only happen if we're out of
memory (and other things will fail) or if we're on the wrong platform
(which is ok).
And remove the DRM_ERRORs from the sprite code itself to avoid dmesg
spam.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
The transcoder port may changed from mode set to mode set, so make sure
to mask out the selection bits before setting the right ones or we'll
get black screens when going from transcoder B to A.
Tested-by: Vincent Vanackere <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
If a PCH pipe PLL is being used by transcoder C, don't disable it.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Add new ioctls for getting and setting the current destination color
key. This allows for simple overlay display control by matching a color
key value in the primary plane before blending the overlay on top.
v2: remove unnecessary mutex acquire/release around reg accesses
v3: add support for full color key management
v4: fix copy & paste bug in snb_get_colorkey
don't bother checking min/max values against docs as the docs are likely
wrong (how could we handle 10bpc surface formats?)
Reviewed-by: Daniel Vetter <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
To save power when the sprite is full screen, we can disable the primary
plane on the same pipe. Track the sprite status and enable/disable the
primary opportunistically.
v2: remove primary plane enable/disable hooks; they're identical
Reviewed-by: Daniel Vetter <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
The video sprites support various video surface formats natively and can
handle scaling as well. So add support for them using the new DRM core
sprite support functions.
v2: use drm specific fourcc header and defines
v3: address Daniel's comments:
- don't take struct mutex around register access (only needed for
regs in the GT power well)
- don't hold struct mutex across vblank waits
- fix up update_plane API (pass obj instead of GTT offset)
- add interlaced defines for sprite regs
- drop unnecessary 'reg' variables
- comment double buffered reg flushing
Also fix w/h confusion when writing the scaling reg.
v4: more fixes, address more comments from Daniel, and include Hai's fix
- prevent divide by zero in scaling calculation (Hai Lan)
- update to Ville's new DRM_FORMAT_* types
- fix sprite watermark handling (calc based on CRTC size, separate
from normal display wm)
- remove private refcounts now that the fb cleanups handles things
v5: add linear surface support
v6: remove color key clearing & setting from update_plane
For this version, I tested DPMS since it came up in the last review;
DPMS off/on works ok when a video player is working under X, but for
power saving we'll probably want to do something smarter. I'll leave
that for a separate patch on top. Likewise with the refcounting/fb
layer handling, which are really separate cleanups.
Reviewed-by: Daniel Vetter <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Each of these error messages can be caused by a broken or malicious
userspace wanting to spam the dmesg with useless info. They're really
not worthy of DRM_DEBUG statements either; those are generally only
useful during bringup of new hardware or versions, and ought to be
removed before going upstream anyway.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
This is actually a core structure with a big future ahead of it. Make
it a little less mysterious.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
This is a core mode setting structure that deserves a little verbiage.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
We never used initial_x/y or the force_encoder_id, so drop those fields
and proide a basic description of the others.
Really, the ELD bits belong in drm_display_info rather than directly in
the connector, but that's a separate cleanup.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Just some basic comments about the place and function of the structure
and fields.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
To properly support the various plane formats supported by different
hardware, the kernel must know the pixel format of a framebuffer object.
So add a new ioctl taking a format argument corresponding to a fourcc
name from the new drm_fourcc.h header file. Implement the fb creation
hooks in terms of the new mode_fb_cmd2 using helpers where the old
bpp/depth values are needed.
v2: create DRM specific fourcc header file for sharing with libdrm etc
v3: fix rebase failure and use DRM fourcc codes in intel_display.c and
update commit message
v4: make fb_cmd2 handle field into an array for multi-object formats
pull in Ville's fix for the memcpy in drm_plane_init
apply Ville's cleanup to zero out fb_cmd2 arg in drm_mode_addfb
v5: add 'flags' field for interlaced support (from Ville)
Signed-off-by: Ville Syrjälä <[email protected]>
Acked-by: Alan Cox <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Planes are a bit like half-CRTCs. They have a location and fb, but
don't drive outputs directly. Add support for handling them to the core
KMS code.
v2: fix ABI of get_plane - move format_type_ptr to the end
v3: add 'flags' field for interlaced support (from Ville)
Acked-by: Alan Cox <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
Reviewed-by: Daniel Vetter <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
We restore the CRTC, encoder, and connector configurations, but if the
mode set failed, the attached display may have been turned off, so we
need to try set_config again to restore things to the way they were.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Misc fixes based on tests with an infoframe analyzer:
- checksum *does* include header bytes
- DIP enable & AVI infoframe are tied together in hw, so disable both
and make sure AVI frames are enabled first
- use every vsync flag for SPD frames to avoid reserved value in
frequency field when enabling both AVI & SPD
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=40281.
Signed-off-by: Jesse Barnes <[email protected]>
Cc: [email protected]
Signed-off-by: Keith Packard <[email protected]>
DPCD 1.1+ adds some automated test infrastructure support. Add support
for reading the IRQ source and jumping to a test handling routine if
needed. Subsequent patches will handle particular tests; this patch
just ACKs any requested tests by default.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Read link status first, followed by the full DPCD receiver cap field
rather than just the first 8 bytes.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Adam Jackson <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Belongs in PCH enable instead. The duplication is worrying and the
specs explicitly list transcoder select *after* actual PLL enable, which
doesn't occur until later.
Signed-off-by: Jesse Barnes <[email protected]>
Tested-By: Eugeni Dodonov <[email protected]>
Reviewed-By: Eugeni Dodonov <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
The watermark reg for the third pipe is in an unusual offset; add
support for it and set watermarks for 3 pipe configs.
Signed-off-by: Jesse Barnes <[email protected]>
Tested-By: Eugeni Dodonov <[email protected]>
Reviewed-By: Eugeni Dodonov <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
At the point where we check, we can't do much about the failure, but it
can aid debugging. Note that the auto-train override bit will be reset
as part of normal mode setting with this patch if a pipe ever does get
stuck, but that's consistent with the workaround for CPT provided by the
hardware team. This patch helped catch the fact that the pipe wasn't
running in the !composite sync FDI case on my IVB SDV, so has already
shown to be useful.
Signed-off-by: Jesse Barnes <[email protected]>
Tested-By: Eugeni Dodonov <[email protected]>
Reviewed-By: Eugeni Dodonov <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Transcoder A will always use PLL A and transcoder B will use PLL B. But
transcoder C could use either, so always mask the select bits off before
or'ing in a new value.
Reported-by: Adam Jackson <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Tested-By: Eugeni Dodonov <[email protected]>
Reviewed-By: Eugeni Dodonov <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
The cursor regs have moved around, add the offsets and new macros for
getting at them.
Signed-off-by: Jesse Barnes <[email protected]>
Tested-By: Eugeni Dodonov <[email protected]>
Reviewed-By: Eugeni Dodonov <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Add two new fields to the intel_crtc struct for 3 pipe support: no_pll
and use_pll_a. The no_pll field is only set on the 3rd pipe to indicate
that it doesn't have a PLL of its own and so shouldn't try to write the
main PLL regs. The use_pll_a field controls which PLL pipe 3 will
share, A or B. The core code will try to share PLLs with whichever pipe
has the same timings, rejecting the mode set if none is found. This
means that pipe 3 must always be set after one of the other pipes has
been configured with real PLL settings.
Signed-off-by: Jesse Barnes <[email protected]>
Tested-By: Eugeni Dodonov <[email protected]>
Reviewed-By: Eugeni Dodonov <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Add a couple of checks now that we're using the 3rd transcoder:
1) make sure the transcoder PLL enable bit is set for the transcoder
in question
2) when checking actual PLL enable, use the selected PLL number rather
than the transcoder number (they could be different now)
Signed-off-by: Jesse Barnes <[email protected]>
Tested-By: Eugeni Dodonov <[email protected]>
Reviewed-By: Eugeni Dodonov <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Well almost anyway. IVB has 3 planes, pipes, transcoders, and FDI
interfaces, but only 2 pipe PLLs. So two of the pipes must use the same
pipe timings (e.g. 2 DP plus one other, or two HDMI with the same mode
and one other, etc.).
Signed-off-by: Jesse Barnes <[email protected]>
Tested-By: Eugeni Dodonov <[email protected]>
Reviewed-By: Eugeni Dodonov <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Add a macro for accessing the two pipe PLLs and add a check to make sure
we don't access a non-existent one in the enable/disable functions.
Signed-off-by: Jesse Barnes <[email protected]>
Tested-By: Eugeni Dodonov <[email protected]>
Reviewed-By: Eugeni Dodonov <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
It's needed for 3 pipe support as well as just regular functionality
(e.g. DisplayPort).
Signed-off-by: Jesse Barnes <[email protected]>
Tested-by: Adam Jackson <[email protected]>
Tested-by: Eugeni Dodonov <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
v2 by danvet: Use a new flag to flush the render target cache on gen6+
(hw reuses the old write flush bit), as suggested by Ben Widawsdy.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Kenneth Graunke <[email protected]>
[danvet: this seems to fix cairo-perf-trace hangs on my snb]
Signed-Off-by: Daniel Vetter <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Prior to Ivybridge, the GFX_MODE would default to 0x800, meaning that
MI_FLUSH would flush the TLBs in addition to the rest of the caches
indicated in the MI_FLUSH command. However starting with Ivybridge, the
register defaults to 0x2800 out of reset, meaning that to invalidate the
TLB we need to use PIPE_CONTROL. Since we're not doing that yet, go
back to the old default so things work.
v2: don't forget to actually *clear* the new bit
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Chris Wilson <[email protected]>
Tested-by: Kenneth Graunke <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
We ought to be calling this from our DPMS routines as well as global
state may change and we need to enable/disable clocks. So split out the
code in preparation for further changes.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
IVB uses the same interrupt reg layout as SNB, so add an IS_GEN7 to the
interrupt debugfs file.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
When enabling turbo, we need to set both the TDC and TDP bits. IIRC
only the TDC one actually matters, but fix it up anyway since the
current code is confusing.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Matthew Garrett <[email protected]>
Expose the SNB+ cache sharing policy register in debugfs. The new file,
i915_cache_sharing, has 4 values, 0-3, with 0 being "max uncore
resources" and 3 being the minimum. Exposing this control should make
benchmarking easier and help us choose a good default.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
This makes it easier to add support for other infoframes (e.g. SPD,
vendor specific).
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Drivers need to know the CEA version number in addition to other display
info (like whether the display is an HDMI sink) before enabling certain
features. So track the CEA version number in the display info
structure.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Before initiating a new read or write on the DP AUX channel, wait for
any outstanding activity to complete. This may happen during normal
retry behavior. If the wait fails (i.e. after 1ms the AUX channel is
still busy) dump a backtrace to make the caller easier to spot.
v2: use msleep instead, and timeout after 3ms (only ever saw 1 retry
with msleep in testing)
v3: fix backtrace check to trigger if the 3ms wait times out
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=38136.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
These bits moved around on SNB and above.
v2: again with the git send-email fail
v3: add macros for getting per-pipe override & enable bits
v4: enable phase sync pointer on SNB and IVB configs as well
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
If a mode set fails we may get a message from drm_crtc_helper if we're lucky,
but it won't tell us anything about *why* we failed to set a mode. So
add a few DRM_ERRORs for the cases that shouldn't happen so we can debug
things more easily.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Mainly for use in debugging and benchmarking, this file allows the user
to control the max frequency used by the GPU. Frequency may still vary
based on workload (if the frequency is set to higher than the minimum)
but won't go over the newly set value.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
On Ironlake and above, we have per-transcoder DIP registers, so use them
for sending DIPs like AVI infoframes on ILK and above.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
CB tuning is needed to handle potential process variations that might
cause clock jitter for certain PLL settings. However, we were setting
it incorrectly since we were using the wrong M value as a check (M1 when
we needed to use the whole M value). Fix it up, making my HDMI
attached display a little prettier (used to have occasional dots crawl
across the display).
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
After writing to the plane control reg we need to write to the surface
reg to trigger the double buffered register latch. On previous
chipsets, writing to DSPADDR was enough, but on ILK+ DSPSURF is the reg
that triggers the double buffer latch.
v2: write DSPADDR too to cover pre-965 chipsets
v3: use flush_display_plane instead, that's what it's for
v4: send the right patch
Signed-off-by: Jesse Barnes <[email protected]>
Tested-by: Keith Packard <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
On CougarPoint and PantherPoint PCH chips, the timing generator may fail
to start after DP training completes. This is due to a bug in the
FDI autotraining detect logic (which will stall the timing generator and
re-enable it once training completes), so disable it to avoid silent DP
mode setting failures.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
If a mode set fails we may get a message from drm_crtc_helper if we're lucky,
but it won't tell us anything about *why* we failed to set a mode. So
add a few DRM_ERRORs for the cases that shouldn't happen so we can debug
things more easily.
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
On sinks with a DPCD rev of 1.1 or greater, we can send sink power
management commands to address 0x600 per section 5.1.5 of the
DisplayPort 1.1a spec.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
When checking link status during a hot plug event or detecting sink
presence, we need to retry 3 times per the spec (section 9.1 of the 1.1a
DisplayPort spec). Consolidate the retry code into a
native_aux_read_retry function for use by get_link_status and _detect.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
We currently use this when a hot plug event is received, only checking
the link status and re-training if we had previously configured a link.
However if we want to preserve the DP configuration across both hot plug
and DPMS events (which we do for userspace apps that don't respond to
hot plug uevents), we need to unconditionally check the link and try to
bring it up on hot plug.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
If ->detect is called too soon after a hot plug event, the sink may not
be ready yet. So try up to 3 times with 1ms sleeps in between tries to
get the data (spec dictates that receivers must be ready to respond within
1ms and that sources should try 3 times).
See section 9.1 of the 1.1a DisplayPort spec.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
When a hotplug event is received, we need to check the receiver cap bits
in case they've changed (as they might with a hub or chain config).
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Jesse Barnes