During noirq suspend phase, mailbox MU irq will be masked
but many drivers still need to communicate with system
controller firmware via mailbox, if MU irq is masked, it
will cause RPC timeout as below:
[ 23.372103] imx-scu scu: RPC send msg timeout
Setting MU irq to be wakeup source is NOT working as GIC
driver does NOT have .irq_set_wake implemented, so to
support suspend/resume, just make imx mailbox driver NOT
suspend, since MU is always a wakeup source on i.MX platforms
with system controller inside, and its power/clock is
maintained by system controller, mailbox driver no need
to manage them.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
i.MX8MQ has clock gate for each GPIO bank, add them
into clock tree for GPIO driver to manage.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
On NXP's i.MX SoCs with system controller inside, CPU frequency
scaling can ONLY be done by system controller firmware, and it
can ONLY be requested from secure mode, so Linux kernel has to
call ARM SMC to trap to ARM-Trusted-Firmware to request system
controller firmware to do CPU frequency scaling.
This patch adds i.MX system controller CPU frequency scaling support,
it reuses cpufreq-dt driver and implement the CPU frequency scaling
inside SCU clock driver.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
On i.MX8MQ platform, clock driver uses platform driver
model and it is probed after GPIO driver, so when GPIO
driver fails to get clock, it should check the error type
to decide whether to return defer probe or just ignore
the clock operation.
Fixes: 2808801aab ("gpio: mxc: add clock operation")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
The i.MX GPT timer driver binding doc is out of date,
update it according to current GPT timer driver.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Now that all sensors supplied by reg_sensors have supported
regulator control, reg_sensors does NOT need to be always ON,
remove "regulator-always-on" to save power.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The mma8451 sensor driver has supported regulators control,
assign the power supplies for mma8451 to enable the control.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The mag3110 sensor driver has supported regulators control,
assign the power supplies for mag3110 to enable the control.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The isl29023 light sensor driver has supported regulator control,
assign the power supply for isl29023 to enable the control.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
This patch adds i.MX system controller RTC set time support, the
RTC set time is implemented via SIP(silicon provider) runtime
service call and ARM-Trusted-Firmware will communicate with system
controller via MU(message unit) IPC to set RTC time.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
During system suspend, the SNVS RTC's clock will be disabled in
noirq suspend phase, but SNVS RTC's alarm interrupt could still
arrive, system will hang if SNVS RTC driver tries to access register
without clock enabled, this patch fixes the issue of this scenario.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
i.MX7ULP is a new SoC of i.MX family which has 8 kbit eFuse OTP,
enable ocotp driver support for this SoC.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
i.MX7ULP SoC's revision info is inside the SIM module,
bit[31:28] of JTAG_ID register defines revision as below
from B0:
0001 B0
0010 B1
This patch adds SoC revision support for i.MX7ULP, test
result as below:
root@imx7ulp-evk ~$ cat /sys/devices/soc0/revision
2.1
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
This patch adds cpuidle support for i.MX7ULP, 3 cpuidle
states supported as below:
1. WFI, just ARM wfi;
2. WAIT mode, mapped to SoC's partial stop mode #3;
3. STOP mode, mapped to SoC's partial stop mode #1.
In WAIT mode, system clock and bus clock will be enabled;
In STOP mode, system clock and bus clock will be disabled.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX6SX has same GPT type as i.MX6DL, in GPT driver, it uses
below TIMER_OF_DECLARE, so the backward compatible should be
"fsl,imx6dl-gpt", correct it.
TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The accelerometer's power supply could be controllable on some
platforms, such as i.MX6Q-SABRESD board, the mma8451's power supplies
are controlled by a GPIO fixed regulator, need to make sure the
regulators are enabled before any communication with mma8451, this
patch adds vdd/vddio regulator operation support.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Martin Kepplinger <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
The accelerometer's power supplies could be controllable on some
platforms, add property "vdd/vddio" power supply to let device tree
to pass phandles to the regulators to driver.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
The light sensor's power supply could be controllable by regulator
on some platforms, such as i.MX6Q-SABRESD board, the light sensor
isl29023's power supply is controlled by a GPIO fixed regulator,
need to make sure the regulator is enabled before any operation of
sensor, this patch adds vcc regulator operation support.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
The magnetometer's power supplies could be controllable on some platforms,
such as i.MX6Q-SABRESD board, the mag3110's power supplies are controlled
by a GPIO fixed regulator, need to make sure the regulators are enabled
before any communication with mag3110, this patch adds vdd/vddio regulator
operation support.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
i.MX7ULP can switch CPU between RUN mode and HSRUN mode
by programming SMC1 register, different clock sources
will be used for CPU in different modes, so SMC1 can be
abstracted as a clock controller for CPU clock switch,
this patch adds support for it.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Put return value checks of calling imx_init_from_nvmem_cells()
into one block to save one condition block for normal case.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Reviewed-by: Daniel Lezcano <[email protected]>
Signed-off-by: Eduardo Valentin <[email protected]>
The thermal driver is a standalone driver for monitoring SoC temperature
by enabling thermal sensor, so it can be enabled even when CONFIG_CPU_FREQ
is NOT set. So remove the dependency with CPU_THERMAL.
Introduce dummy function of legacy cooling register/unregister to make
thermal driver probe successfully when CONFIG_CPU_FREQ is NOT set.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Reviewed-by: Daniel Lezcano <[email protected]>
Signed-off-by: Eduardo Valentin <[email protected]>
i.MX PWM module's ipg_clk_s is for PWM register access, on most of i.MX
SoCs, this ipg_clk_s is from system ipg clock or perclk which is always
enabled, but on i.MX7D, the ipg_clk_s is from PWM1_CLK_ROOT which is
controlled by CCGR132, that means the CCGR132 MUST be enabled first
before accessing PWM registers on i.MX7D. This patch adds ipg clock
operation to make sure register access successfully on i.MX7D and it
fixes Linux kernel boot up hang during PWM driver probe.
Fixes: 4a23e6ee9f ("ARM: dts: imx7d-sdb: Restore pwm backlight support")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and secure rtc etc..
This patch adds i.MX system controller RTC driver support,
Linux kernel has to communicate with system controller via MU
(message unit) IPC to set/get RTC time and other alarm functions,
since the RTC set time needs to be done in secure EL3 mode (required
by system controller firmware) and alarm functions needs to be done
with general MU IRQ handle, these depend on other components which
are NOT ready, so this patch ONLY enables the RTC time read.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller, the system controller is in charge of system
power, clock and secure RTC etc. management, Linux kernel
has to communicate with system controller via MU (message unit)
IPC to do RTC operation, this patch adds binding doc for i.MX
system controller RTC driver.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
i.MX TPM needs "ipg" clock for register access and "per" clock for
timer function, the driver gets "ipg" clock by searching the clock
name, but timer-of initialization will get first clock in device
tree TPM node since no clock name specified in of_clk, that means
the "per" clock MUST be the first clock entry in device tree TPM
node, this patch specifies clock name for of_clk to avoid this
restriction, it makes TPM driver work properly with different sequence
of clock entries in device tree TPM node.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Convert the driver to use the timer_of helpers. This allows to handle
timer base, clock and irq using common timer_of driver and it
simplifies the code.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
This patch allows building and compile-testing the i.MX GPT driver
also for ARM64. The delay_timer is only supported on ARMv7.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode
or HSRUN mode, it is controlled in SMC1 module. The RUN
mode and HSRUN mode will use different clock source for
ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN
mode, so the control bits in SMC1 module can be abstracted
as a HW clock mux, this patch adds HSRUN mode related
clocks in SCG1 module and adds "arm" clock in SMC1 module
to support RUN mode and HSRUN mode switch.
Latest clock tree in RUN mode as below:
firc 0 0 0 48000000 0 0 50000
firc_bus_clk 0 0 0 48000000 0 0 50000
hsrun_scs_sel 0 0 0 48000000 0 0 50000
hsrun_divcore 0 0 0 48000000 0 0 50000
sosc 3 3 3 24000000 0 0 50000
spll_pre_sel 1 1 1 24000000 0 0 50000
spll_pre_div 1 1 2 24000000 0 0 50000
spll 1 1 2 528000000 0 0 50000
spll_pfd0 1 1 1 500210526 0 0 50000
spll_pfd_sel 1 1 0 500210526 0 0 50000
spll_sel 1 1 0 500210526 0 0 50000
scs_sel 1 1 0 500210526 0 0 50000
divcore 1 1 0 500210526 0 0 50000
arm 1 1 0 500210526 0 0 50000
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
There are HSRUN mode clock mux and divider in SCG1 module,
and SMC1 can control i.MX7ULP CPU to run in RUN mode or
HSRUN mode, the mode switch bits are actually a clock mux,
add these clocks for clock driver and dtb to use.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks
gate in CCM_CCGR0 register, add them into clock tree for
clock management.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Same as other i.MX6 SoCs, ensure unused MMDC channel's
handshake is bypassed, this is to make sure no request
signal will be generated when periphe_clk_sel is changed
or SRC warm reset is triggered.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Add isl29023 light sensor support on i2c3 bus, the light
sensor's power is controlled by a fixed regulator, since
the isl29023 driver and most of other sensors on same
board like mag3110 and mma8451 do NOT support regulator
operation currently, they are all controlled by this
regulator, so this patch also adds the fixed regulator
support and make it always on.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Add egalax touch screen support on i2c2 bus, it is connected
to LVDS0, while the existing one on i2c3 bus is connected to
LVDS1.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX6SLL EVK board has WDOG_B pin connected to the PMIC;
Add the WDOG_B pinctrl entry and 'fsl,ext-reset-output'
property to wdog node to let watchdog trigger a system
POR reset via the PMIC.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
On i.MX6SLL EVK board, there is a debug LED controlled
by MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 pin, add support
for it.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Current imx7d-sdb.dts has some incorrect settings about
Rev-A and Rev-B boards, some of the settings are based on
Rev-A board but some are based on Rev-B board, clean up it
by adding i.MX7D SDB Rev-A board support, make default
imx7d-sdb.dts for Rev-B board as usual, and introduce
imx7d-sdb-reva.dts for Rev-A board. Below are the affected
differences of Rev-A and Rev-B board:
Rev-A Rev-B
USB_OTG2_PWR: UART3_CTS_B GPIO1_IO07
ENET_EN_B: None GPIO1_IO04
TP_INT_B: EPDC_DATA13 EPDC_BDR1
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
From i.MX6SX reference manual CCM chapter, KPP and
WDOGn use IPG clock as their clock, specify IPG
clock for KPP and WDOGn instead of DUMMY clock.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Remove "regulator-always-on" property for vddpu regulator
since it can be OFF when GPU power domain is OFF.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The "fsl,mf-mix-wakeup-irq" is ONLY used as a temporary
solution in NXP's internal tree for Mega/Fast Mix off
feature after suspend, upstream kernel does NOT need it,
remove it.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The sw2iso count should cover ARM LDO ramp-up time,
the MAX ARM LDO ramp-up time may be up to more than
100us on some boards, this patch sets sw2iso to 0xf
(~384us) which is the reset value, and it is much
more safe to cover different boards, since we have
observed that some customer boards failed with current
setting of 0x2.
Fixes: 05136f0897 ("ARM: imx: support arm power off in cpuidle for i.mx6sx")
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Put return value checks of calling imx6ul_opp_check_speed_grading()
into one block to save one condition block for normal case.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
In voltage scale down path, the return value is NOT
used at all, remove them to simplify the code.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
During noirq suspend/resume phase, GPIO irq could arrive
and its registers like IMR will be changed by irq handle
process, to make the GPIO registers exactly when it is
powered ON after resume, move the GPIO noirq suspend/resume
callback to syscore suspend/resume phase, local irq is
disabled at this phase so GPIO registers are atomic.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Add return value check for voltage scale when ARM clock
rate change fail.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
There are clock assignments in all i.MX7D dtb files for UART1,
below is the example in imx7d-sdb.dts, so setting UART1 clock
in clock driver is NOT necessary, actually, module clocks setting
should be done in module driver.
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
};
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
During probe phase, the error path can be handled in one place and
use goto method to save many duplicated code.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Daniel Lezcano <[email protected]>
Signed-off-by: Eduardo Valentin <[email protected]>
i.MX6Q has MMDC0 ipg clock in CCM CCGR, add it into
clock tree for clock management.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
i.MX6SL has MMDC0 and MMDC1 ipg clock in CCM CCGR, add them into
clock tree for clock management.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
i.MX6SLL has MMDC1 ipg clock in CCM CCGR, add it into
clock tree for clock management.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
i.MX6SX has MMDC1 ipg clock in CCM CCGR, add it into
clock tree for clock management.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
i.MX6UL has MMDC1 ipg clock in CCM CCGR, add it into
clock tree for clock management.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
i.MX7D uses virtual cpu clock of "arm" clock to be child clock
of "arm_a7_root_clk" and it is with CLK_IS_CRITICAL flag set, so
no need to add CLK_IS_CRITICAL flag for keeping "arm_a7_root_clk"
use count correct, latest clock tree is as below in clk_summary:
pll_arm_main 1 1 0 792000000 0
pll_arm_main_bypass 1 1 0 792000000 0
pll_arm_main_clk 1 1 0 792000000 0
arm_a7_src 1 1 0 792000000 0
arm_a7_cg 1 1 0 792000000 0
arm_a7_div 1 1 0 792000000 0
arm_a7_root_clk 1 1 0 792000000 0
arm 1 1 0 792000000
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Add CLK_IS_CRITICAL flag for cpu clock type to
make cpu clock use count correct, as cpu clock
should be always critical.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
On i.MX7D, IMX7D_NAND_USDHC_BUS_ROOT_CLK is NOT necessary
for system, and IMX7D_AHB_CHANNEL_ROOT_CLK is NOT existing
at all, remove them from clks_init_on array.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
On i.MX6UL/i.MX6ULL, accessing OCOTP directly is wrong because
the ocotp clock needs to be enabled first. Add support for reading
OCOTP through the nvmem API, and keep the old method there to
support old dtb.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
Some i.MX platforms like i.MX7S/D uses generic ARM cpuidle
driver and psci method to support cpuidle feature, select
CONFIG_ARM_CPUIDLE by default for such platforms.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX8MQ and i.MX8MM share same gpc module with i.MX7D, they
can reuse gpcv2 pgc driver for power domain control, this
patch renames all functions and structure definitions started
with "imx7" to "imx", and use .data in imx_gpcv2_dt_ids[] to
pass platform specific power domain data for power domain
driver, thus make gpcv2 pgc driver more generic for i.MX
platforms.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Andrey Smirnov <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
gpcv2 driver is NOT just used on i.MX7D which has Cortex-A7
cores, but also on i.MX8MQ/i.MX8MM platforms which use Cortex-A53
cores, so let's use A_CORE instread of A7 to avoid confusion.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Andrey Smirnov <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The i.MX 6ULZ processor is a high-performance, ultra
cost-efficient consumer Linux processor featuring an
advanced implementation of a single Arm® Cortex®-A7 core,
which operates at speeds up to 900 MHz.
This patch adds basic MSL support for i.MX6ULZ, the
i.MX6ULZ has same soc_id as i.MX6ULL, and SRC_SBMR2 bit[6]
is to differentiate i.MX6ULZ from i.MX6ULL, 1'b1 means
i.MX6ULZ and 1'b0 means i.MX6ULL.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The i.MX7 SRC's compatible string should be "fsl,imx7d-src".
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first, so use the nvmem-cells binding instead.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Update VDD_SOC voltage to 1.25V for 900MHz operating point
according to datasheet Rev. 1.3, 08/2018, 25mV is added to
the minimum allowed values to cover power supply ripple.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Sébastien Szymanski <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
This patch adds wakeup function support for egalax touch
screen, if "wakeup-source" is added to device tree's egalax
touch screen node, the wakeup function will be enabled, and
egalax touch screen will be able to wakeup system from suspend.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Dmitry Torokhov <[email protected]>
On some i.MX SoCs' low power mode, such as i.MX7D's LPSR(low power
state retention), UART iomux settings will be lost, need to add
pinctrl sleep/default mode switch during suspend/resume to make
sure UART iomux settings are correct after resume.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
In noirq suspend/resume stage with no_console_suspend enabled,
imx_uart_console_write() may be called to print out log_buf
message by printk(), so there will be race condition between
imx_uart_console_write() and imx_uart_save/restore_context(),
need to add lock to protect the registers save/restore operations.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
i.MX6ULL is a lite version of i.MX6UL, its full name
is i.MX6 UltraLiteLite, NOT UlltraLite.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX6SLL has GPIO clock gates in CCM CCGR, add
clock property for GPIO driver to make sure all
GPIO banks work as expected.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The i.MX7ULP B0 chip has some pin changes for USB and VIU
module, update pinfunc header file accordingly.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Add "gpio-ranges" property to establish connections between GPIOs
and PINs on i.MX6SLL pinctrl driver, for details, please refer to
Documentation/devicetree/bindings/gpio/gpio.txt of "gpio-ranges"
property.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
When thermal zone is in passive mode, disabling its mode from
sysfs is NOT taking effect at all, it is still polling the
temperature of the disabled thermal zone and handling all thermal
trips, it makes user confused. The disabling operation should
disable the thermal zone behavior completely, for both active and
passive mode, this patch clears the passive_delay when thermal
zone is disabled and restores it when it is enabled.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Eduardo Valentin <[email protected]>
GPIO registers could lose context on i.MX7D, when
enter LPSR mode, the whole SoC will be powered off
except LPSR domain, GPIO banks will lose context
in this case, need to restore the context after
resume from LPSR mode.
This patch adds new compatible string for i.MX7D
which supports GPIO power off feature in suspend,
and adds the GPIO save/restore operations in noirq
suspend/resume phase, since GPIO is fundamental
module which could be used by other peripherals'
resume phase.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
i.MX6SX has a 16KB always-on ocram bank called
ocram_s, and its clock gate in CCM CCGR1 CG14
needs to be enabled before access, add it to
clock tree.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Commit b97872d4eb ("ARM: dts: imx: Add missing OPP properties for CPUs")
added "operating-points" property for all CPUs, but i.MX7D already has
"operating-points-v2" property on both CPUs, so no need to add
"operating-points" property again, this patch removes it.
Fixes: b97872d4eb ("ARM: dts: imx: Add missing OPP properties for CPUs")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
On i.MX6SLL EVK board, pfuze100 sw4 supplies
LPDDR3 which is critical for system, must be
always on.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Anson Huang