For defer probe error, no need to output error message which
will cause confusion.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Add clock driver support for i.MX8MP which is a new SoC of i.MX8M
family.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Switch the imx_clk_gate4_flags() function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to
move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Memory address/size depends on board design, so memory node should
be in board DT.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Daniel Baluta <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Memory address/size depends on board design, so memory node should
be in board DT.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Daniel Baluta <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The vdd3p0 LDO's input should be from external USB VBUS directly, NOT
PMIC's power supply, the vdd3p0 LDO's target output voltage can be
controlled by SW, and it requires input voltage to be high enough, with
incorrect power supply assigned, if the power supply's voltage is lower
than the LDO target output voltage, it will return fail and skip the LDO
voltage adjustment, so remove the power supply assignment for vdd3p0 to
avoid such scenario.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The vdd3p0 LDO's input should be from external USB VBUS directly, NOT
PMIC's power supply, the vdd3p0 LDO's target output voltage can be
controlled by SW, and it requires input voltage to be high enough, with
incorrect power supply assigned, if the power supply's voltage is lower
than the LDO target output voltage, it will return fail and skip the LDO
voltage adjustment, so remove the power supply assignment for vdd3p0 to
avoid such scenario.
Fixes: 96a9169cf6 ("ARM: dts: imx6sll-evk: Assign corresponding power supply for vdd3p0")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The vdd3p0 LDO's input should be from external USB VBUS directly, NOT
PMIC's power supply, the vdd3p0 LDO's target output voltage can be
controlled by SW, and it requires input voltage to be high enough, with
incorrect power supply assigned, if the power supply's voltage is lower
than the LDO target output voltage, it will return fail and skip the LDO
voltage adjustment, so remove the power supply assignment for vdd3p0 to
avoid such scenario.
Fixes: 3feea8805d ("ARM: dts: imx6sl-evk: Assign corresponding power supply for LDOs")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The vdd3p0 LDO's input should be from external USB VBUS directly, NOT
PMIC's power supply, the vdd3p0 LDO's target output voltage can be
controlled by SW, and it requires input voltage to be high enough, with
incorrect power supply assigned, if the power supply's voltage is lower
than the LDO target output voltage, it will return fail and skip the LDO
voltage adjustment, so remove the power supply assignment for vdd3p0 to
avoid such scenario.
Fixes: 37a4bdead1 ("ARM: dts: imx6sx-sdb: Assign corresponding power supply for LDOs")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The vdd3p0 LDO's input should be from external USB VBUS directly, NOT
PMIC's power supply, the vdd3p0 LDO's target output voltage can be
controlled by SW, and it requires input voltage to be high enough, with
incorrect power supply assigned, if the power supply's voltage is lower
than the LDO target output voltage, it will return fail and skip the LDO
voltage adjustment, so remove the power supply assignment for vdd3p0 to
avoid such scenario.
Fixes: 93385546ba ("ARM: dts: imx6qdl-sabresd: Assign corresponding power supply for LDOs")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Add i.MX8MP to blacklist, so that imx-cpufreq-dt driver can handle
speed grading bits just like other i.MX8M SoCs.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Viresh Kumar <[email protected]>
When reading key state from SCU, the response data from SCU firmware
is 4 bytes due to MU message protocol, but ONLY the first byte is the
key state, other 3 bytes could be some dirty data, so we should ONLY
take the first byte as key state to avoid reporting incorrect state.
Signed-off-by: Anson Huang <[email protected]>
Fixes: 688f1dfb69 ("Input: keyboard - imx_sc: Add i.MX system controller key support")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dmitry Torokhov <[email protected]>
ARM_ERRATA_814220 has below description:
The v7 ARM states that all cache and branch predictor maintenance
operations that do not specify an address execute, relative to
each other, in program order.
However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation.
This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
r0p4, r0p5.
i.MX6UL and i.MX7D have Cortex-A7 r0p5 inside, need to enable
ARM_ERRATA_814220 for proper workaround.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX7ULP's unique ID layout in OCOTP is different from other
i.MX6/7 SoCs as below:
OCOTP layout unique ID
0x4b0 bit[15:0] bit[15:0]
0x4c0 bit[15:0] bit[31:16]
0x4d0 bit[15:0] bit[47:32]
0x4e0 bit[15:0] bit[63:48]
Add support for reading serial number from OCOTP on i.MX7ULP.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
gic is appointed as default interrupt parent for devices, so no need
to specify it again in device nodes which use it as interrupt parent.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Machine compatible string normally is located in board DT, remove
the duplicated one from SoC dtsi.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Daniel Baluta <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Machine compatible string normally is located in board DT, remove
the duplicated one from SoC dtsi.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Daniel Baluta <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Use platform_get_irq_byname_optional() and platform_get_irq_optional()
instead of platform_get_irq_byname() and platform_get_irq() for optional
IRQs to avoid below error message during probe:
[ 0.795803] fec 30be0000.ethernet: IRQ pps not found
[ 0.800787] fec 30be0000.ethernet: IRQ index 3 not found
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Fugang Duan <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Failed to get irq using name is NOT fatal as driver will use index
to get irq instead, use platform_get_irq_byname_optional() instead
of platform_get_irq_byname() to avoid below error message during
probe:
[ 0.819312] fec 30be0000.ethernet: IRQ int0 not found
[ 0.824433] fec 30be0000.ethernet: IRQ int1 not found
[ 0.829539] fec 30be0000.ethernet: IRQ int2 not found
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Fugang Duan <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
i.MX8MN LPDDR4 EVK board shares most of the device as DDR4 EVK board,
the ONLY difference are the DDR type and PMIC, add support for it
and make it default i.MX8MN EVK board as usual.
The PMIC driver is NOT ready, so cpu-freq needs to be disabled as
it depends on regulator provided by PMIC.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX8MN has different EVK boards to support different DDR types,
the ONLY differences are DDR chips and PMIC, so most of the devices
can be shared between these EVK boards, create a EVK dtsi file for
common use.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The soc_device_attribute structure already contains a serial_number
attribute to show SoC's unique ID, just use it to show SoC's unique
ID instead of creating a new file called soc_uid.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The soc_device_attribute structure already contains a serial_number
attribute to show SoC's unique ID, just use it to show SoC's unique
ID instead of creating a new file called soc_uid.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX6/7 SoCs have a 64-bit SoC unique ID stored in OCOTP,
it can be used as SoC serial number, add this support for
i.MX6Q/6DL/6SL/6SX/6SLL/6UL/6ULL/6ULZ/7D, see below example
on i.MX6Q:
root@imx6qpdlsolox:~# cat /sys/devices/soc0/serial_number
240F31D4E1FDFCA7
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
On i.MX6UL 14x14 EVK board, mag3110's power is controlled by
sensor regulator, assign power supplies for mag3110 driver
to do power management.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Node name is supposed to be generic, use "magnetometer" instead
of "mag3110" for magnetometer node.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
On i.MX6UL 14x14 EVK board, sensors' power are controlled
by GPIO5_IO02, add GPIO regulator for sensors to manage
their power.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX GPT driver ONLY supports 1 instance, i.MX6UL already has
GPT1 enabled by default, so GPT2 should be disabled.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The cooling device properties "#cooling-cells" should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in the
CPU node it is trying to bring up, so that it can register a cooling
device.
Add such missing properties.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The cooling device properties "#cooling-cells" should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in the
CPU node it is trying to bring up, so that it can register a cooling
device.
Add such missing properties.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The cooling device properties "#cooling-cells" should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in the
CPU node it is trying to bring up, so that it can register a cooling
device.
Add such missing properties.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
In the latest reference manual Rev.0,06/2019, the DDR clock mux
is extended to 2 bits, and the clock options are also changed,
correct them accordingly.
Fixes: b1260067ac ("clk: imx: add imx7ulp clk driver")
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
On i.MX8MQ EVK board, VDD_ARM is from a DC-DC converter which
is always ON, the GPIO1_IO13 is ONLY to switch VDD_ARM's voltage
between 0.9V and 1V for CPU DVFS, so VDD_ARM's GPIO regulator
should be always ON to avoid below confusion after kernel boot
up:
imx8mqevk login:
[ 31.776619] vdd_arm: disabling
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Add scu key node for i.MX8QXP, disabled by default as it
depends on board design.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX8MN has different speed grade definition compared to
i.MX8MQ/i.MX8MM, when fuses are NOT written, the default
speed_grade should be set to minimum available OPP defined
in DT which is 1.2GHz, the corresponding speed_grade value
should be 0xb.
Fixes: 5b8010ba70 ("cpufreq: imx-cpufreq-dt: Add i.MX8MN support")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Viresh Kumar <[email protected]>
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and scu key etc..
Adds i.MX system controller key driver support, Linux kernel has
to communicate with system controller via MU (message unit) IPC
to get scu key's status.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dmitry Torokhov <[email protected]>
All nodes are better to follow alphabetical sort except iomuxc
which has huge pinctrl data, better to put it at the end of
file.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Adjust some nodes to make them follow alphabetical sort except
iomuxc node which is put at the end of file because of its huge
pinctrl data.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The iomuxc node is being put at end of file because of its huge
pinctrl data. I2C devices should be placed in alphabetical sort.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
On i.MX8MQ, usdhc's ipg clock is from IMX8MQ_CLK_IPG_ROOT,
assign it explicitly instead of using IMX8MQ_CLK_DUMMY.
Fixes: 748f908cc8 ("arm64: add basic DTS for i.MX8MQ")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The SCU firmware does NOT always have return value stored in message
header's function element even the API has response data, those special
APIs are defined as void function in SCU firmware, so they should be
treated as return success always.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX7S/D's GPT ipg clock should be from GPT clock root and
controlled by CCM's GPT CCGR, using correct clock source for
GPT ipg clock instead of IMX7D_CLK_DUMMY.
Fixes: 3ef79ca6bd ("ARM: dts: imx7d: use imx7s.dtsi as base device tree")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
All i.MX SoCs except i.MX1 have ONLY one necessary IRQ, use
platform_get_irq_optional() to get second/third IRQ which are
optional to avoid below error message during probe:
[ 0.726219] imx-uart 30860000.serial: IRQ index 1 not found
[ 0.731329] imx-uart 30860000.serial: IRQ index 2 not found
Fixes: 7723f4c5ec ("driver core: platform: Add an error message to platform_get_irq*()")
Signed-off-by: Anson Huang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Add "opp-suspend" property for i.MX7D to make sure system
suspend with max available opp.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Leonard Crestez <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Use "fsl,imx8mm-ocotp" as i.MX8MN ocotp's fallback compatible instead
of "fsl,imx7d-ocotp" to support SoC UID read, as i.MX8MN reuses
i.MX8MM's SoC ID driver.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Compared to i.MX7D, i.MX8MM has different ocotp layout, so it should
NOT use "fsl,imx7d-ocotp" as ocotp's fallback compatible, remove it.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
i.MX8MN DDR4 EVK board has a GPIO LED to indicate status,
add support for it.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Use common 1413X/1416X PLL clock structure to save a lot
of duplicated code on i.MX8MN clock driver.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Leonard Crestez <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Many i.MX8M SoCs use same 1443X/1416X PLL, such as i.MX8MM,
i.MX8MN and later i.MX8M SoCs, moving these PLL definitions
to pll14xx driver can save a lot of duplicated code on each
platform.
Meanwhile, no need to define PLL clock structure for every
module which uses same type of PLL, e.g., audio/video/dram use
1443X PLL, arm/gpu/vpu/sys use 1416X PLL, define 2 PLL clock
structure for each group is enough.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Leonard Crestez <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The SCU firmware API for getting UID should have response,
otherwise, the message stored in function stack could be
released and then the response data received from SCU will be
stored into that released stack and cause kernel NULL pointer
dump.
Fixes: 73feb4d0f8 ("soc: imx-scu: Add SoC UID(unique identifier) support")
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
On some of i.MX SoCs like i.MX8QXP, there is ONLY one IRQ for each
GPIO bank, so it is better to check the IRQ count before getting
second IRQ to avoid below error message during probe:
[ 1.070908] gpio-mxc 5d080000.gpio: IRQ index 1 not found
[ 1.077420] gpio-mxc 5d090000.gpio: IRQ index 1 not found
[ 1.083766] gpio-mxc 5d0a0000.gpio: IRQ index 1 not found
[ 1.090122] gpio-mxc 5d0b0000.gpio: IRQ index 1 not found
[ 1.096470] gpio-mxc 5d0c0000.gpio: IRQ index 1 not found
[ 1.102804] gpio-mxc 5d0d0000.gpio: IRQ index 1 not found
[ 1.109144] gpio-mxc 5d0e0000.gpio: IRQ index 1 not found
[ 1.115475] gpio-mxc 5d0f0000.gpio: IRQ index 1 not found
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The i.MX7ULP Watchdog Timer (WDOG) module is an independent timer
that is available for system use.
It provides a safety feature to ensure that software is executing
as planned and that the CPU is not stuck in an infinite loop or
executing unintended code. If the WDOG module is not serviced
(refreshed) within a certain period, it resets the MCU.
Add driver support for i.MX7ULP watchdog.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
The RTC IRQ is requested before the struct rtc_device is allocated,
this may lead to a NULL pointer dereference in IRQ handler.
To fix this issue, allocating the rtc_device struct before requesting
the RTC IRQ using devm_rtc_allocate_device, and use rtc_register_device
to register the RTC device.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
Some platforms like i.MX8M series SoCs have clock control for TMU,
add optional clocks property to the binding doc.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Zhang Rui <[email protected]>
Use __maybe_unused for power management related functions
instead of #if CONFIG_PM_SLEEP to simply the code.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Zhang Rui <[email protected]>
Use devm_platform_ioremap_resource() instead of of_iomap() to
save the iounmap() call in error handle path;
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Zhang Rui <[email protected]>
When registering tmu zone failed, the error path should be err_tmu
instead of err_iomap, as iounmap() needs to be called.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Zhang Rui <[email protected]>
Some platforms like i.MX8MQ has clock control for this module,
need to add clock operations to make sure the driver is working
properly.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Guido Günther <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Zhang Rui <[email protected]>
Anson Huang