Add a 1ms delay after reset deactivation. Otherwise the chip returns
bogus ID value. This is observed with 88E6390 (Peridot) chip.
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Merge commit 1c8c5a9d38 ("Merge
git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next") undid the
fix from commit 36f9814a49 ("bpf: fix uapi hole for 32 bit compat
applications") by taking the gpl_compatible 1-bit field definition from
commit b85fab0e67 ("bpf: Add gpl_compatible flag to struct
bpf_prog_info") as is. That breaks architectures with 16-bit alignment
like m68k. Add 31-bit pad after gpl_compatible to restore alignment of
following fields.
Thanks to Dmitry V. Levin his analysis of this bug history.
Signed-off-by: Baruch Siach <[email protected]>
Acked-by: Song Liu <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: Daniel Borkmann <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Cc: Linus Torvalds <[email protected]>
Signed-off-by: Daniel Borkmann <[email protected]>
The Clearfog GT-8K board is capable of supplying power up to 2W to SFP
modules. Make that explicit in the device-tree. Without this property
current kernel does not allow SFP modules that require more than 1W.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Don't disable the ipg clock in the regulator error path. The clock is
disable unconditionally two lines below the failed_regulator label.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
The Linaro hosted git tree is no longer active. Update the cpufreq
entry.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Viresh Kumar <[email protected]>
Revert commit 3d71746c42 ("PCI: armada8k: Add support for gpio controlled
reset signal").
That commit breaks boot on Macchiatobin board when a Mellanox NIC is
present in the PCIe slot.
It turns out that full reset cycle requires first comphy serdes
initialization. Reset signal toggle without comphy initialization makes
access to PCI configuration registers stall indefinitely. U-Boot toggles
the Macchiatobin PCIe reset line already at boot, after initializing the
comphy serdes.
So while commit 3d71746c42 ("PCI: armada8k: Add support for gpio controlled
reset signal") enables PCIe on platforms that U-Boot does not touch the
reset line (like Clearfog GT-8K), it breaks PCIe (and boot) on the
Macchiatobin board.
Revert commit 3d71746c42 ("PCI: armada8k: Add support for gpio controlled
reset signal") entirely to fix the Macchiatobin regression.
Reported-by: Sven Auhagen <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
struct gpio_chip documentation recommends to always implement this
callback function.
A more concrete motivation is to be able (in combination with
GPIOD_ASIS) to detect whether the bootloader has changed the state of a
GPIO signal.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
The MPP52 signal is on the seconds GPIO instance of CP0, which
corresponds to the &cp0_gpio2 handle.
Rename the property name to the standard '-gpios' suffix while at it.
Fixes: b83e1669ad ("arm64: dts: marvell: mcbin: add support for PCIe")
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Add support for the gpio reset signal binding as described in the
designware-pcie.txt DT binding document. Both the documented
'reset-gpio' property name and the more standard 'reset-gpios' name are
supported.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Thomas Petazzoni <[email protected]>
The external nWDOG signal connects to the EVK board reset circuit.
Tested on the i.MX8MQ EVK rev B3.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Lucas Stach <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
The RTC_VL_READ ioctl reports the low battery condition. Still,
pcf8523_rtc_read_time() happily returns invalid dates in this case.
Check the battery health on pcf8523_rtc_read_time() to avoid that.
Reported-by: Erik Čuk <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
Enable the USB3 peripheral that is wired to CON2 on the Clearfog GT-8K
board.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
This reverts commit 8ed4636877.
This commit breaks boot on Armada 8K based systems. Reverting it makes
affected systems boot again.
Reported-by: Sergey Matyukevich <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
The mvpp2_phylink_validate() relies on the interface field of
phylink_link_state to determine valid link modes. However, when called
from phylink_sfp_module_insert() this field in not initialized. The
default switch case then excludes 10G link modes. This allows 10G SFP
modules that are detected correctly to be configured at max rate of
2.5G.
Catch the uninitialized PHY mode case, and allow 10G rates.
Fixes: d97c9f4ab0 ("net: mvpp2: 1000baseX support")
Cc: Maxime Chevallier <[email protected]>
Cc: Antoine Tenart <[email protected]>
Acked-by: Russell King <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Deassert the reset and wireless disable signals on the CON2 mini-PCIe
socket. That allows the host to detect USB devices on the mini-PCIe
socket.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
This reset signal controls the Marvell 1512 1G PHY.
Note that current implementation queries the PHY over the MDIO bus
(get_phy_device() call from of_mdiobus_register_phy()) before reset
signal deassert. If the PHY reset signal is asserted at boot time, PHY
registration fails. So current code relies on the bootloader to deassert
the reset signal.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
The fixed regulator driver ignores the gpio flags, so this change has
no practical effect in the current implementation. Fix it anyway to
correct the hardware description.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
The link modes that sfp_parse_support() detects are stored in the
'modes' bitmap. There is no reason to make an exception for 1000Base-PX
or 1000Base-BX10.
Fixes: 03145864bd ("sfp: support 1G BiDi (eg, FiberStore SFP-GE-BX) modules")
Signed-off-by: Baruch Siach <[email protected]>
Acked-by: Russell King <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
The abracon,tc-resistor property value is in kOhm.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
When connecting SFP PHY to phylink use the detected interface.
Otherwise, the link fails to come up when the configured 'phy-mode'
differs from the SFP detected mode.
Move most of phylink_connect_phy() into __phylink_connect_phy(), and
leave phylink_connect_phy() as a wrapper. phylink_sfp_connect_phy() can
now pass the SFP detected PHY interface to __phylink_connect_phy().
This fixes 1GB SFP module link up on eth3 of the Macchiatobin board that
is configured in the DT to "2500base-x" phy-mode.
Fixes: 9525ae8395 ("phylink: add phylink infrastructure")
Suggested-by: Russell King <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
This adds support for the PCIe interface on the CON4 mini-PCIe
connector.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
The SolidRun Clearfog GT-8K is based on Marvell Armada 8040 SoC.
https://wiki.solid-run.com/doku.php?id=products:a8040:clearfoggt8k
The following devices were tested with this DT on top of kernel
v4.19-rc4:
* 1GB Ethernet WAN
* 4 ports 1GB Ethernet switch (2.5GB uplink)
* SFP port
* SATA on CON3 PCIe slot
* USB3 type A port
* SD card and eMMC
* 2 LEDs
* 2 push buttons
[gregory: fix block comment alignement]
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
The vmmc phandle, like all power supply property names, must have the
'-supply' suffix.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Without a valid of_node in struct device we can't find the mvpp2 port
device by its DT node. Specifically, this breaks
of_find_net_device_by_node().
For example, the Armada 8040 based Clearfog GT-8K uses Marvell 88E6141
switch connected to the &cp1_eth2 port:
&cp1_mdio {
...
switch0: switch0@4 {
compatible = "marvell,mv88e6085";
...
ports {
...
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp1_eth2>;
};
};
};
};
Without this patch, dsa_register_switch() returns -EPROBE_DEFER because
of_find_net_device_by_node() can't find the device_node of the &cp1_eth2
device.
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
This enables support for SFP cages on SolidRun Armada 38x platforms.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Use savedefconfig to sync defconfig for current kernel. No change in
generated configuration.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
When the RTC block looses power it needs a reset sequence to make it
usable again. Otherwise, writes to the time register have no effect.
This reset sequence combines information from the mvebu_rtc driver in
the Marvell provided U-Boot, and the SolidRun provided U-Boot repo.
Tested on the Armada 388 based SolidRun Clearfog Base.
Signed-off-by: Baruch Siach <[email protected]>
Acked-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
Commit 2f28e4c24b (thermal: armada: Clarify control registers
accesses) introduced the new thermal binding. The new binding extends
the second registers field size to 8. Switch to the new binding to fix
thermal reading values. Without this change the fix for errata #132698
introduced in commit 8c0b888f66 (thermal: armada: Change sensors trim
default value) has no effect.
Cc: [email protected] # v4.16+
Reviewed-by: Miquel Raynal <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Don't warn about missing interrupts support when the parent interrupt is
not defined. Enabling interrupts support would not make it work anyway.
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
The current device-tree description of the SolidRun Armada 38x platforms
has been successfully tested with production systems.
Signed-off-by: Baruch Siach <[email protected]>
Acked-by: Jon Nettleton <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
The SolidRun Armada 388 SOM has the SPI flash populated by default
unless the customer explicitly asks otherwise. Enable support by
default.
Signed-off-by: Baruch Siach <[email protected]>
Acked-by: Russell King <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
The i.MX UART peripheral uses the RST_B signal as input, and CTS_B as
output. This is just like the DCE role in RS-232. This is true
regardless of the "DTE mode" setting of this peripheral.
As a result, rs485 support hardware must use the CTS_B signal to control
the RS-485 transceiver. This is in contrast to generic rs485 kernel
code, documentation, and DT property names that consistently refer to
the RTS as transceiver control signal.
Add a note in the DT binding document about that, to reduce the
confusion somewhat.
Signed-off-by: Baruch Siach <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
The right most SFP connector on the Macchiatobin board and schematics is
marked as CON13/CON14.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
ixjuser.h includes the telephony.h header. Other than that no kernel
code uses any of these headers. The last user of the ixjuser.h header
has been removed in commit 7326446c72 (Staging: remove telephony
drivers), more than 5 years ago.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Commit 7ed915059c (gpio: raspberrypi-ext: fix firmware dependency)
fixed the Kconfig dependency to ensure that gpio-raspberrypi-exp is not
built-in when the firmware is a module. But the Kconfig syntax for doing
so is cryptic. Add a comment to make it a little easier.
Cc: Arnd Bergmann <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
There is no pinctrl_usbotg_2 node in current Hummingboard dts files.
Drop reference to that.
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
This allows adding devices for which the firmware exposes control interface
via the mailbox. An example of such device is the GPIO expander.
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Signed-off-by: Eric Anholt <[email protected]>
The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware over
I2C. The firmware mailbox interface allows the ARM core to control the
GPIO lines.
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Add latest firmware property tags from the latest Raspberry Pi downstream
kernel. This is needed for the GPIO tags, so we can control the GPIO
multiplexor lines.
Acked-by: Stefan Wahren <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
A 'C' was missing in the model name, this patch fixes it.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Add description of the J25 and J27 UART headers of the Macchiatobin. They use
uart peripherals that the CP0 (J25) and CP1 (J27) provide.
Even though J25 and J27 are labeled as UART header, the pins on these headers
can be muxed for other purposes. But the UART functionality is useful when the
board is mounted in an ATX style enclosure, since the console UART is not
accessible through the microUSB at CON9.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
The CP110 component has 4 uart peripherals. All of them use the same clock
gate for slow peripherals that is shared with the i2c and spi peripherals.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Indent the numbered item with one space like all other items in the same
list.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Tejun Heo <[email protected]>
The CP110 component is integrated in the Armada 8k and 7k lines of
processors.
Signed-off-by: Baruch Siach <[email protected]>
[<[email protected]>: renamed the register pointers as
well as some definitions related to the new register names and
simplified the init sequence for Armada 380]
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Gregory CLEMENT <[email protected]>
Tested-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Eduardo Valentin <[email protected]>
The AP806 component is integrated in the Armada 8K and 7K lines of
processors.
The thermal sensor sample field on the status register is a signed
value. Extend armada_get_temp() and the driver structure to handle
signed values.
Signed-off-by: Baruch Siach <[email protected]>
[<[email protected]>: Changes when applying over the
previous patches, including the register names changes, also switched
the coefficients values to s64 instead of unsigned long to deal with
negative values and used do_div instead of the traditionnal '/']
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Gregory CLEMENT <[email protected]>
Tested-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Eduardo Valentin <[email protected]>
Use msleep for long (> 10ms) delays, instead of the busy waiting mdelay.
All delays are called from the probe routine, where scheduling is
allowed.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Eduardo Valentin <[email protected]>
Add compatible strings for AP806 and CP110 that are part of the Armada
8k/7k line of SoCs.
Add a note on the differences in the size of the control area in
different bindings. This is an existing difference between the Armada
375 binding and the other boards already supported. The new AP806 and
CP110 bindings are similar to the existing Armada 375 in this regard.
Signed-off-by: Baruch Siach <[email protected]>
[<[email protected]>: reword, additional details]
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Eduardo Valentin <[email protected]>
The formula implementation at armada_get_temp() indicates that the sign
in the formula is inverted.
Cc: Ezequiel Garcia <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Eduardo Valentin <[email protected]>
Extend the container size to 0x2000 to include the gpio controller at
offset 0x1040.
While at it, add start address notation to the gpio node name to match
its 'offset' property.
Fixes: 63dac0f492 ("arm64: dts: marvell: add gpio support for Armada
7K/8K")
Cc: <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
The SPI_IOC_MESSAGE() macro references _IOC_SIZEBITS. Add linux/ioctl.h
to make sure this macro is defined. This fixes the following build
failure of lcdproc with the musl libc:
In file included from .../sysroot/usr/include/sys/ioctl.h:7:0,
from hd44780-spi.c:31:
hd44780-spi.c: In function 'spi_transfer':
hd44780-spi.c:89:24: error: '_IOC_SIZEBITS' undeclared (first use in this function)
status = ioctl(p->fd, SPI_IOC_MESSAGE(1), &xfer);
^
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Cc: [email protected]
Make the Rx rate select control gpio property name match the documented
binding. This would make the addition of 'rate-select1-gpios' for SFP+
support more natural.
Also, make the MOD-DEF0 gpio property name match the documentation.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Add device-tree binding documentation SFP transceivers. Support for SFP
transceivers has been recently introduced (drivers/net/phy/sfp.c).
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
This complements commit 9a94b3a4bd (dt-binding: phy: don't confuse with
Ethernet phy properties).
The generic PHY 'phys' property sometime appears in the same node with
the Ethernet PHY 'phy' or 'phy-handle' properties. Add a warning in
ethernet.txt to reduce confusion.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
The generic PHY 'phys' property sometime appears in the same node with
the Ethernet PHY 'phy' or 'phy-handle' properties. Add a warning in
phy-bindings.txt to reduce confusion.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Commit b053dc5a72 (powerpc: Refactor device tree binding) split the
Ethernet PHY binding documentation out of the big booting-without-of.txt
file, leaving a dangling reference to "section 2" in the 'interrupts'
property description. Drop that reference, and make the description look
more like the rest.
While at it, make the example interrupt-parent phandle look more like a
real world phandle, and use an IRQ_TYPE_ macro for the 'interrupts'
type.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
The size field of the memory node is wrong. Rely on the default value in
sama5d2.dtsi that happens to be correct for the SAMA5D2 Xplained board.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Alexandre Belloni <[email protected]>
Don't print the version at the beginning of atmel_spi_probe(). This avoids
spamming the log whenever a deferred probe runs.
Signed-off-by: Baruch Siach <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
An alias name should have an index number even when it is the only of its type.
This allows U-Boot to add the local-mac-address property. Otherwise U-Boot
skips the alias.
Fixes: 6a93792774 ("ARM: bcm2835: dt: Add the ethernet to the device trees")
Signed-off-by: Baruch Siach <[email protected]>
Acked-by: Lubomir Rintel <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
According to the BCM2835 ARM Peripherals document uart1 doesn't map to pins
36-39, but uart0 does.
Also, split into separate Rx/Tx and CST/RTS groups to match other uart nodes.
Fixes: 21ff843931 ("ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.")
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
According to the BCM2835 ARM Peripherals document i2c0 doesn't map to pins 32,
34 but to 28, 29.
Fixes: 21ff843931 ("ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.")
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Downstream kernel uses pins 32, 33 as UART0 (PL011) Rx/Tx to communicate with
the Bluetooth chip. So ALT3 of these pins is most likely not CTS/RTS. Change
the node name to reflect that. This matches section 6.2 "Alternative Function
Assignments" in the BCM2835 ARM Peripherals document.
With this change in place, adding
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
};
to bcm2837-rpi-3-b.dts does the right thing on my Raspberry Pi 3.
Pins 30, 31 are CTS/RTS of UART0 in alternate function 3. Rename uart0_gpio30
as well.
While at it, fix a little typo in a nearby comment.
Fixes: 21ff843931 ("ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.")
Acked-by: Stefan Wahren <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Since commit f9b6b0ef60 ("selftests: move vDSO tests from Documentation/vDSO")
parse_vdso.c moved under selftests. Update the reference to match.
Cc: Jonathan Corbet <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Jonathan Corbet <[email protected]>
The email address of Jan Dumon bounces, and there is not relevant information
in the linked website.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
The Freescale provided imx-vpu looks for firmware files under /lib/firmware/vpu
by default. Make coda look there for firmware files to ease the update path.
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
The loop over the ov2659_formats[] array just a few lines above
verifies that mf->code matches the selected array entry.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Hans Verkuil <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
The asynchronous API is quite mature. Not mentioning is at all is probably
better than saying it is under development.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
__LINUX_IF_ETHER_H is not defined anywhere, and if_ether.h can keep itself from
double inclusion, though it uses a single underscore prefix.
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
The Orion GPIO controller binding description in mrvl-gpio.txt is obsolete, and
duplicates the description in gpio-mvebu.txt.
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
The Orion GPIO controller binding description in mrvl-gpio.txt is obsolete, and
duplicates the description in gpio-mvebu.txt.
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
spidev.h uses _IOC_SIZEBITS directly. musl libc does not provide this macro
unless linux/ioctl.h is included explicitly. Fixes build failures like:
In file included from .../host/usr/arm-buildroot-linux-musleabihf/sysroot/usr/include/sys/ioctl.h:7:0,
from .../build/spidev_test-v3.15/spidev_test.c:20:
.../build/spidev_test-v3.15/spidev_test.c: In function ‘transfer’:
.../build/spidev_test-v3.15/spidev_test.c:75:18: error: ‘_IOC_SIZEBITS’ undeclared (first use in this function)
ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
^
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
This website is obsolete, as it has not been updated in more than a decade.
Cc: "Theodore Ts'o" <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Some RS-232 to RS-485 transceivers require Rx to be disabled on Tx to
avoid echo of Tx data into the Rx buffer. Specifically, the XR3160E
RS-232/RS-485/RS-422 transceiver behaves this way.
This commit disables Rx on active Tx when SER_RS485_ENABLED is active and
SER_RS485_RX_DURING_TX is disabled.
Note that this is a change in behavior of the driver. Until now
SER_RS485_RX_DURING_TX was enabled unconditionally even when disabled in
the TIOCSRS485 ioctl serial_rs485 flags field.
Cc: Uwe Kleine-König <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
The per adapter bus_lock already projects from concurrent calls to the
master_xfer callback. No need to add a driver internal lock.
Also, rephrase a comment to drop mention of this lock.
Reported-by: Rongrong Zou <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Acked-by: Mika Westerberg <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
Baruch Siach